diff options
| author | David A. Mellis <d.mellis@arduino.cc> | 2012-09-13 10:41:16 -0400 |
|---|---|---|
| committer | David A. Mellis <d.mellis@arduino.cc> | 2012-09-13 10:41:16 -0400 |
| commit | 0d9a111face4f3629bcae8e52af843792af3b453 (patch) | |
| tree | 7cc1b8c1b0c1acb7c90a75f258ce036dac494b17 /firmwares/wifishield/wifi_dnld | |
Moving into firmwares directory.
Diffstat (limited to 'firmwares/wifishield/wifi_dnld')
69 files changed, 38811 insertions, 0 deletions
diff --git a/firmwares/wifishield/wifi_dnld/.cproject b/firmwares/wifishield/wifi_dnld/.cproject new file mode 100644 index 0000000..286dad7 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/.cproject @@ -0,0 +1,1281 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<?fileVersion 4.0.0?> + +<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> +<storageModule moduleId="org.eclipse.cdt.core.settings"> +<cconfiguration id="avr32.managedbuild.config.gnu.exe.debug.618344773"> +<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="avr32.managedbuild.config.gnu.exe.debug.618344773" moduleId="org.eclipse.cdt.core.settings" name="Debug"> +<externalSettings/> +<extensions> +<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/> +<extension id="com.atmel.avr.toolchain.avr32gcc.elf32-avr32" point="org.eclipse.cdt.core.BinaryParser"/> +<extension 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+</cconfiguration> +</storageModule> +<storageModule moduleId="cdtBuildSystem" version="4.0.0"> +<project id="wifi_dnld.avr32.managedbuild.target.gnu.exe_2.0.1.570559459" name="32-bit AVR/GNU Executable" projectType="avr32.managedbuild.target.gnu.exe_2.0.1"/> +</storageModule> +</cproject> diff --git a/firmwares/wifishield/wifi_dnld/.project b/firmwares/wifishield/wifi_dnld/.project new file mode 100644 index 0000000..aa3047b --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/.project @@ -0,0 +1,70 @@ +<?xml version="1.0" encoding="UTF-8"?> +<projectDescription> + <name>wifi_dnld</name> + <comment></comment> + <projects> + </projects> + <buildSpec> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> + <triggers>clean,full,incremental,</triggers> + <arguments> + <dictionary> + <key>?name?</key> + <value></value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.append_environment</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildArguments</key> + <value></value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildCommand</key> + <value>make</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.buildLocation</key> + <value>${workspace_loc:/wifi_dnld/Debug}</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.contents</key> + <value>org.eclipse.cdt.make.core.activeConfigSettings</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableAutoBuild</key> + <value>false</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableCleanBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableFullBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.stopOnError</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key> + <value>true</value> + </dictionary> + </arguments> + </buildCommand> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> + <arguments> + </arguments> + </buildCommand> + </buildSpec> + <natures> + <nature>com.atmel.avr32.core.nature</nature> + <nature>org.eclipse.cdt.core.cnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> + </natures> +</projectDescription> diff --git a/firmwares/wifishield/wifi_dnld/Release/wifi_dnld.elf b/firmwares/wifishield/wifi_dnld/Release/wifi_dnld.elf Binary files differnew file mode 100644 index 0000000..11ec3dd --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/Release/wifi_dnld.elf diff --git a/firmwares/wifishield/wifi_dnld/src/CONFIG/conf_access.h b/firmwares/wifishield/wifi_dnld/src/CONFIG/conf_access.h new file mode 100644 index 0000000..23e9b34 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/CONFIG/conf_access.h @@ -0,0 +1,170 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Memory access control configuration file. + * + * This file contains the possible external configuration of the memory access + * control. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _CONF_ACCESS_H_ +#define _CONF_ACCESS_H_ + +#include "compiler.h" +#include "board.h" + + +/*! \name Activation of Logical Unit Numbers + */ +//! @{ +#define LUN_0 DISABLE //!< On-Chip Virtual Memory. +#define LUN_1 ENABLE //!< AT45DBX Data Flash. +#define LUN_2 DISABLE //!< SD/MMC Card over SPI. +#define LUN_3 DISABLE +#define LUN_4 DISABLE +#define LUN_5 DISABLE +#define LUN_6 DISABLE +#define LUN_7 DISABLE +#define LUN_USB DISABLE //!< Host Mass-Storage Memory. +//! @} + +/*! \name LUN 0 Definitions + */ +//! @{ +#define VIRTUAL_MEM LUN_0 +#define LUN_ID_VIRTUAL_MEM LUN_ID_0 +#define LUN_0_INCLUDE "virtual_mem.h" +#define Lun_0_test_unit_ready virtual_test_unit_ready +#define Lun_0_read_capacity virtual_read_capacity +#define Lun_0_wr_protect virtual_wr_protect +#define Lun_0_removal virtual_removal +#define Lun_0_usb_read_10 virtual_usb_read_10 +#define Lun_0_usb_write_10 virtual_usb_write_10 +#define Lun_0_mem_2_ram virtual_mem_2_ram +#define Lun_0_ram_2_mem virtual_ram_2_mem +#define LUN_0_NAME "\"On-Chip Virtual Memory\"" +//! @} + +/*! \name LUN 1 Definitions + */ +//! @{ +#define AT45DBX_MEM LUN_1 +#define LUN_ID_AT45DBX_MEM LUN_ID_1 +#define LUN_1_INCLUDE "at45dbx_mem.h" +#define Lun_1_test_unit_ready at45dbx_test_unit_ready +#define Lun_1_read_capacity at45dbx_read_capacity +#define Lun_1_wr_protect at45dbx_wr_protect +#define Lun_1_removal at45dbx_removal +#define Lun_1_usb_read_10 at45dbx_usb_read_10 +#define Lun_1_usb_write_10 at45dbx_usb_write_10 +#define Lun_1_mem_2_ram at45dbx_df_2_ram +#define Lun_1_ram_2_mem at45dbx_ram_2_df +#define LUN_1_NAME "\"AT45DBX Data Flash\"" +//! @} + +/*! \name LUN 2 Definitions + */ +//! @{ +#define SD_MMC_SPI_MEM LUN_2 +#define LUN_ID_SD_MMC_SPI_MEM LUN_ID_2 +#define LUN_2_INCLUDE "sd_mmc_spi_mem.h" +#define Lun_2_test_unit_ready sd_mmc_spi_test_unit_ready +#define Lun_2_read_capacity sd_mmc_spi_read_capacity +#define Lun_2_wr_protect sd_mmc_spi_wr_protect +#define Lun_2_removal sd_mmc_spi_removal +#define Lun_2_usb_read_10 sd_mmc_spi_usb_read_10 +#define Lun_2_usb_write_10 sd_mmc_spi_usb_write_10 +#define Lun_2_mem_2_ram sd_mmc_spi_mem_2_ram +#define Lun_2_ram_2_mem sd_mmc_spi_ram_2_mem +#define LUN_2_NAME "\"SD/MMC Card over SPI\"" +//! @} + +/*! \name USB LUNs Definitions + */ +//! @{ +#define MEM_USB LUN_USB +#define LUN_ID_MEM_USB LUN_ID_USB +#define LUN_USB_INCLUDE "host_mem.h" +#define Lun_usb_test_unit_ready(lun) host_test_unit_ready(lun) +#define Lun_usb_read_capacity(lun, nb_sect) host_read_capacity(lun, nb_sect) +#define Lun_usb_read_sector_size(lun) host_read_sector_size(lun) +#define Lun_usb_wr_protect(lun) host_wr_protect(lun) +#define Lun_usb_removal() host_removal() +#define Lun_usb_mem_2_ram(addr, ram) host_read_10_ram(addr, ram) +#define Lun_usb_ram_2_mem(addr, ram) host_write_10_ram(addr, ram) +#define LUN_USB_NAME "\"Host Mass-Storage Memory\"" +//! @} + +/*! \name Actions Associated with Memory Accesses + * + * Write here the action to associate with each memory access. + * + * \warning Be careful not to waste time in order not to disturb the functions. + */ +//! @{ +#define memory_start_read_action(nb_sectors) +#define memory_stop_read_action() +#define memory_start_write_action(nb_sectors) +#define memory_stop_write_action() +//! @} + +/*! \name Activation of Interface Features + */ +//! @{ +#define ACCESS_USB DISABLED //!< MEM <-> USB interface. +#define ACCESS_MEM_TO_RAM ENABLED //!< MEM <-> RAM interface. +#define ACCESS_STREAM DISABLED //!< Streaming MEM <-> MEM interface. +#define ACCESS_STREAM_RECORD DISABLED //!< Streaming MEM <-> MEM interface in record mode. +#define ACCESS_MEM_TO_MEM DISABLED //!< MEM <-> MEM interface. +#define ACCESS_CODEC DISABLED //!< Codec interface. +//! @} + +/*! \name Specific Options for Access Control + */ +//! @{ +#define GLOBAL_WR_PROTECT DISABLED //!< Management of a global write protection. +//! @} + + +#endif // _CONF_ACCESS_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/CONFIG/conf_at45dbx.h b/firmwares/wifishield/wifi_dnld/src/CONFIG/conf_at45dbx.h new file mode 100644 index 0000000..3280e4f --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/CONFIG/conf_at45dbx.h @@ -0,0 +1,83 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT45DBX configuration file. + * + * This file contains the possible external configuration of the AT45DBX. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an SPI module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _CONF_AT45DBX_H_ +#define _CONF_AT45DBX_H_ + + +#include "conf_access.h" + +#if AT45DBX_MEM == DISABLE + #error conf_at45dbx.h is #included although AT45DBX_MEM is disabled +#endif + + +#include "at45dbx.h" + + +//_____ D E F I N I T I O N S ______________________________________________ + +//! Size of AT45DBX data flash memories to manage. +#define AT45DBX_MEM_SIZE AT45DBX_1MB + +//! Number of AT45DBX components to manage. +#define AT45DBX_MEM_CNT 1 + +//! First chip select used by AT45DBX components on the SPI module instance. +//! AT45DBX_SPI_NPCS0_PIN always corresponds to this first NPCS, whatever it is. +#define AT45DBX_SPI_FIRST_NPCS AT45DBX_SPI_NPCS + +//! SPI master speed in Hz. +#define AT45DBX_SPI_MASTER_SPEED 12000000 + +//! Number of bits in each SPI transfer. +#define AT45DBX_SPI_BITS 8 + + +#endif // _CONF_AT45DBX_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/Doc/SPB104 product brief.pdf b/firmwares/wifishield/wifi_dnld/src/Doc/SPB104 product brief.pdf Binary files differnew file mode 100644 index 0000000..8705cb1 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/Doc/SPB104 product brief.pdf diff --git a/firmwares/wifishield/wifi_dnld/src/Doc/gettingstarted.pdf b/firmwares/wifishield/wifi_dnld/src/Doc/gettingstarted.pdf Binary files differnew file mode 100644 index 0000000..7c37693 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/Doc/gettingstarted.pdf diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/ASM/trampoline.x b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/ASM/trampoline.x new file mode 100644 index 0000000..c127121 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/ASM/trampoline.x @@ -0,0 +1,74 @@ +/* This file is part of the ATMEL AVR32-SoftwareFramework-AT32UC3A-1.4.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AVR32 UC3 ISP trampoline. + * + * In order to be able to program a project with both BatchISP and JTAGICE mkII + * without having to take the general-purpose fuses into consideration, add this + * file to the project and change the program entry point to _trampoline. + * + * The pre-programmed ISP will be erased if JTAGICE mkII is used. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32UC devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "conf_isp.h" + + +//! @{ +//! \verbatim + + + // This must be linked @ 0x80000000 if it is to be run upon reset. + .section .reset, "ax", @progbits + + + .global _trampoline + .type _trampoline, @function +_trampoline: + // Jump to program start. + rjmp program_start + + .org PROGRAM_START_OFFSET +program_start: + // Jump to the C runtime startup routine. + lda.w pc, _stext + + +//! \endverbatim +//! @} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/ARDUINO/arduino.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/ARDUINO/arduino.h new file mode 100644 index 0000000..fbdd466 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/ARDUINO/arduino.h @@ -0,0 +1,234 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1100 board header file. + * + * This file contains definitions and services related to the features of the + * EVK1100 board rev. B and C. + * + * To use this board, define BOARD=EVK1100. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _ARDUINO_H_ +#define _ARDUINO_H_ + +#include "compiler.h" + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. +# include "led.h" +#endif // __AVR32_ABI_COMPILER__ + + +/*! \name Oscillator Definitions + */ +//! @{ + +// RCOsc has no custom calibration by default. Set the following definition to +// the appropriate value if a custom RCOsc calibration has been applied to your +// part. +//#define FRCOSC AVR32_PM_RCOSC_FREQUENCY //!< RCOsc frequency: Hz. + +#define FOSC32 32768 //!< Osc32 frequency: Hz. +#define OSC32_STARTUP AVR32_PM_OSCCTRL32_STARTUP_8192_RCOSC //!< Osc32 startup time: RCOsc periods. + +#define FOSC0 12000000 //!< Osc0 frequency: Hz. +#define OSC0_STARTUP AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC //!< Osc0 startup time: RCOsc periods. + +// Osc1 crystal is not mounted by default. Set the following definitions to the +// appropriate values if a custom Osc1 crystal is mounted on your board. +//#define FOSC1 12000000 //!< Osc1 frequency: Hz. +//#define OSC1_STARTUP AVR32_PM_OSCCTRL1_STARTUP_2048_RCOSC //!< Osc1 startup time: RCOsc periods. + +//! @} + + +//! Number of LEDs. +#define LED_COUNT 3 + +/*! \name GPIO Connections of LEDs + */ +//! @{ +#define LED0_GPIO AVR32_PIN_PB19 +#define LED1_GPIO AVR32_PIN_PB20 +#define LED2_GPIO AVR32_PIN_PB21 +//! @} + +/*! \name PWM Channels of LEDs + */ +//! @{ +#define LED0_PWM 0 +#define LED1_PWM 1 +#define LED2_PWM 2 +//! @} + +/*! \name PWM Functions of LEDs + */ +//! @{ +#define LED0_PWM_FUNCTION AVR32_PWM_0_FUNCTION +#define LED1_PWM_FUNCTION AVR32_PWM_1_FUNCTION +#define LED2_PWM_FUNCTION AVR32_PWM_2_FUNCTION +//! @} + +/*! \name Color Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#define LED_MONO0_GREEN LED0 +#define LED_MONO1_GREEN LED1 +#define LED_MONO2_GREEN LED2 +//! @} + +#if 0 +/*! \name SPI Connections of the DIP204 LCD + */ +//! @{ +#define DIP204_SPI (&AVR32_SPI1) +#define DIP204_SPI_NPCS 2 +#define DIP204_SPI_SCK_PIN AVR32_SPI1_SCK_0_0_PIN +#define DIP204_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_0_FUNCTION +#define DIP204_SPI_MISO_PIN AVR32_SPI1_MISO_0_0_PIN +#define DIP204_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_0_FUNCTION +#define DIP204_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_0_PIN +#define DIP204_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_0_FUNCTION +#define DIP204_SPI_NPCS_PIN AVR32_SPI1_NPCS_2_0_PIN +#define DIP204_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_2_0_FUNCTION +//! @} + +/*! \name GPIO and PWM Connections of the DIP204 LCD Backlight + */ +//! @{ +#define DIP204_BACKLIGHT_PIN AVR32_PIN_PB18 +#define DIP204_PWM_CHANNEL 6 +#define DIP204_PWM_PIN AVR32_PWM_6_PIN +#define DIP204_PWM_FUNCTION AVR32_PWM_6_FUNCTION +//! @} +#endif + +/*! \name SPI Connections of the AT45DBX Data Flash Memory + */ +//! @{ +#define AT45DBX_SPI (&AVR32_SPI1) +#define AT45DBX_SPI_NPCS 2 +#define AT45DBX_SPI_SCK_PIN AVR32_SPI1_SCK_0_0_PIN +#define AT45DBX_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_0_FUNCTION +#define AT45DBX_SPI_MISO_PIN AVR32_SPI1_MISO_0_0_PIN +#define AT45DBX_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_0_FUNCTION +#define AT45DBX_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_0_PIN +#define AT45DBX_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_0_FUNCTION +#define AT45DBX_SPI_NPCS2_PIN AVR32_SPI1_NPCS_2_0_PIN +#define AT45DBX_SPI_NPCS2_FUNCTION AVR32_SPI1_NPCS_2_0_FUNCTION +#define AT45DBX_CHIP_RESET AVR32_PIN_PA02 +//! @} + + +/*! \name GPIO and SPI Connections of the SD/MMC Connector + */ +//! @{ +//#define SD_MMC_CARD_DETECT_PIN AVR32_PIN_PA02 +//#define SD_MMC_WRITE_PROTECT_PIN AVR32_PIN_PA07 +#define SD_MMC_SPI (&AVR32_SPI1) +#define SD_MMC_SPI_NPCS 1 +#define SD_MMC_SPI_SCK_PIN AVR32_SPI1_SCK_0_0_PIN +#define SD_MMC_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_0_FUNCTION +#define SD_MMC_SPI_MISO_PIN AVR32_SPI1_MISO_0_0_PIN +#define SD_MMC_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_0_FUNCTION +#define SD_MMC_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_0_PIN +#define SD_MMC_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_0_FUNCTION +#define SD_MMC_SPI_NPCS_PIN AVR32_SPI1_NPCS_1_0_PIN +#define SD_MMC_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_1_0_FUNCTION +//! @} + +/* Timer Counter to generate clock for WiFi chip*/ +# define WIFI_TC (&AVR32_TC) +# define WIFI_TC_CHANNEL_ID 0 +# define WIFI_TC_CHANNEL_PIN AVR32_TC_A0_0_0_PIN +# define WIFI_TC_CHANNEL_FUNCTION AVR32_TC_A0_0_0_FUNCTION +// Note that TC_A0_0_0 pin is pin 6 (PB23) on AT32UC3A1512 QFP100. + +/* Pin related to WiFi chip communication */ +#ifndef USE_POLL + #define USE_POLL +#endif + #define SPI_CS 0 + #define AVR32_SPI AVR32_SPI1 + #define GPIO_IRQ_PIN AVR32_PIN_PA03 + #define GPIO_IRQ AVR32_GPIO_IRQ_7 + #define GPIO_W_RESET_PIN AVR32_PIN_PA07 + #define GPIO_W_SHUTDOWN_PIN AVR32_PIN_PA09 + +/* Pin related to shield communication */ + #define ARDUINO_HANDSHAKE_PIN AVR32_PIN_PA25 + + #define AVR32_PDCA_PID_TX AVR32_PDCA_PID_SPI1_TX + #define AVR32_PDCA_PID_RX AVR32_PDCA_PID_SPI1_RX + + +#if 0 +/*! \name TWI Connections of the Spare TWI Connector + */ +//! @{ +#define SPARE_TWI (&AVR32_TWI) +#define SPARE_TWI_SCL_PIN AVR32_TWI_SCL_0_0_PIN +#define SPARE_TWI_SCL_FUNCTION AVR32_TWI_SCL_0_0_FUNCTION +#define SPARE_TWI_SDA_PIN AVR32_TWI_SDA_0_0_PIN +#define SPARE_TWI_SDA_FUNCTION AVR32_TWI_SDA_0_0_FUNCTION +//! @} + + +/*! \name SPI Connections of the Spare SPI Connector + */ +//! @{ +#define SPARE_SPI (&AVR32_SPI0) +#define SPARE_SPI_NPCS 0 +#define SPARE_SPI_SCK_PIN AVR32_SPI0_SCK_0_0_PIN +#define SPARE_SPI_SCK_FUNCTION AVR32_SPI0_SCK_0_0_FUNCTION +#define SPARE_SPI_MISO_PIN AVR32_SPI0_MISO_0_0_PIN +#define SPARE_SPI_MISO_FUNCTION AVR32_SPI0_MISO_0_0_FUNCTION +#define SPARE_SPI_MOSI_PIN AVR32_SPI0_MOSI_0_0_PIN +#define SPARE_SPI_MOSI_FUNCTION AVR32_SPI0_MOSI_0_0_FUNCTION +#define SPARE_SPI_NPCS_PIN AVR32_SPI0_NPCS_0_0_PIN +#define SPARE_SPI_NPCS_FUNCTION AVR32_SPI0_NPCS_0_0_FUNCTION +//! @} +#endif + +#endif // _ARDUINO_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/ARDUINO/led.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/ARDUINO/led.c new file mode 100644 index 0000000..d7cd439 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/ARDUINO/led.c @@ -0,0 +1,346 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1100 board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the EVK1100 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include <avr32/io.h> +#include "preprocessor.h" +#include "compiler.h" +#include "arduino.h" +#include "led.h" + + +//! Structure describing LED hardware connections. +typedef const struct +{ + struct + { + U32 PORT; //!< LED GPIO port. + U32 PIN_MASK; //!< Bit-mask of LED pin in GPIO port. + } GPIO; //!< LED GPIO descriptor. + struct + { + S32 CHANNEL; //!< LED PWM channel (< 0 if N/A). + S32 FUNCTION; //!< LED pin PWM function (< 0 if N/A). + } PWM; //!< LED PWM descriptor. +} tLED_DESCRIPTOR; + + +//! Hardware descriptors of all LEDs. +static tLED_DESCRIPTOR LED_DESCRIPTOR[LED_COUNT] = +{ +#define INSERT_LED_DESCRIPTOR(LED_NO, unused) \ + { \ + {LED##LED_NO##_GPIO / 32, 1 << (LED##LED_NO##_GPIO % 32)},\ + {LED##LED_NO##_PWM, LED##LED_NO##_PWM_FUNCTION } \ + }, + MREPEAT(LED_COUNT, INSERT_LED_DESCRIPTOR, ~) +#undef INSERT_LED_DESCRIPTOR +}; + + +//! Saved state of all LEDs. +static volatile U32 LED_State = (1 << LED_COUNT) - 1; + + +U32 LED_Read_Display(void) +{ + return LED_State; +} + + +void LED_Display(U32 leds) +{ + // Use the LED descriptors to get the connections of a given LED to the MCU. + tLED_DESCRIPTOR *led_descriptor; + volatile avr32_gpio_port_t *led_gpio_port; + + // Make sure only existing LEDs are specified. + leds &= (1 << LED_COUNT) - 1; + + // Update the saved state of all LEDs with the requested changes. + LED_State = leds; + + // For all LEDs... + for (led_descriptor = &LED_DESCRIPTOR[0]; + led_descriptor < LED_DESCRIPTOR + LED_COUNT; + led_descriptor++) + { + // Set the LED to the requested state. + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + if (leds & 1) + { + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= 1; + } +} + + +U32 LED_Read_Display_Mask(U32 mask) +{ + return Rd_bits(LED_State, mask); +} + + +void LED_Display_Mask(U32 mask, U32 leds) +{ + // Use the LED descriptors to get the connections of a given LED to the MCU. + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // Make sure only existing LEDs are specified. + mask &= (1 << LED_COUNT) - 1; + + // Update the saved state of all LEDs with the requested changes. + Wr_bits(LED_State, mask, leds); + + // While there are specified LEDs left to manage... + while (mask) + { + // Select the next specified LED and set it to the requested state. + led_shift = 1 + ctz(mask); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + leds >>= led_shift - 1; + if (leds & 1) + { + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= 1; + mask >>= led_shift; + } +} + + +Bool LED_Test(U32 leds) +{ + return Tst_bits(LED_State, leds); +} + + +void LED_Off(U32 leds) +{ + // Use the LED descriptors to get the connections of a given LED to the MCU. + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // Make sure only existing LEDs are specified. + leds &= (1 << LED_COUNT) - 1; + + // Update the saved state of all LEDs with the requested changes. + Clr_bits(LED_State, leds); + + // While there are specified LEDs left to manage... + while (leds) + { + // Select the next specified LED and turn it off. + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +void LED_On(U32 leds) +{ + // Use the LED descriptors to get the connections of a given LED to the MCU. + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // Make sure only existing LEDs are specified. + leds &= (1 << LED_COUNT) - 1; + + // Update the saved state of all LEDs with the requested changes. + Set_bits(LED_State, leds); + + // While there are specified LEDs left to manage... + while (leds) + { + // Select the next specified LED and turn it on. + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +void LED_Toggle(U32 leds) +{ + // Use the LED descriptors to get the connections of a given LED to the MCU. + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // Make sure only existing LEDs are specified. + leds &= (1 << LED_COUNT) - 1; + + // Update the saved state of all LEDs with the requested changes. + Tgl_bits(LED_State, leds); + + // While there are specified LEDs left to manage... + while (leds) + { + // Select the next specified LED and toggle it. + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrt = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +U32 LED_Read_Display_Field(U32 field) +{ + return Rd_bitfield(LED_State, field); +} + + +void LED_Display_Field(U32 field, U32 leds) +{ + // Move the bit-field to the appropriate position for the bit-mask. + LED_Display_Mask(field, leds << ctz(field)); +} + + +U8 LED_Get_Intensity(U32 led) +{ + tLED_DESCRIPTOR *led_descriptor; + + // Check that the argument value is valid. + led = ctz(led); + led_descriptor = &LED_DESCRIPTOR[led]; + if (led >= LED_COUNT || led_descriptor->PWM.CHANNEL < 0) return 0; + + // Return the duty cycle value if the LED PWM channel is enabled, else 0. + return (AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)) ? + AVR32_PWM.channel[led_descriptor->PWM.CHANNEL].cdty : 0; +} + + +void LED_Set_Intensity(U32 leds, U8 intensity) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_pwm_channel_t *led_pwm_channel; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // For each specified LED... + for (leds &= (1 << LED_COUNT) - 1; leds; leds >>= led_shift) + { + // Select the next specified LED and check that it has a PWM channel. + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + if (led_descriptor->PWM.CHANNEL < 0) continue; + + // Initialize or update the LED PWM channel. + led_pwm_channel = &AVR32_PWM.channel[led_descriptor->PWM.CHANNEL]; + if (!(AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL))) + { + led_pwm_channel->cmr = (AVR32_PWM_CPRE_MCK << AVR32_PWM_CPRE_OFFSET) & + ~(AVR32_PWM_CALG_MASK | + AVR32_PWM_CPOL_MASK | + AVR32_PWM_CPD_MASK); + led_pwm_channel->cprd = 0x000000FF; + led_pwm_channel->cdty = intensity; + AVR32_PWM.ena = 1 << led_descriptor->PWM.CHANNEL; + } + else + { + AVR32_PWM.isr; + while (!(AVR32_PWM.isr & (1 << led_descriptor->PWM.CHANNEL))); + led_pwm_channel->cupd = intensity; + } + + // Switch the LED pin to its PWM function. + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + if (led_descriptor->PWM.FUNCTION & 0x1) + { + led_gpio_port->pmr0s = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->pmr0c = led_descriptor->GPIO.PIN_MASK; + } + if (led_descriptor->PWM.FUNCTION & 0x2) + { + led_gpio_port->pmr1s = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->pmr1c = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->gperc = led_descriptor->GPIO.PIN_MASK; + } +} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/ARDUINO/led.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/ARDUINO/led.h new file mode 100644 index 0000000..a577124 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/ARDUINO/led.h @@ -0,0 +1,191 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1100 board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the EVK1100 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _LED_H_ +#define _LED_H_ + +#include "compiler.h" + + +/*! \name Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#define LED0 0x01 +#define LED1 0x02 +#define LED2 0x04 +#define LED3 0x08 +#define LED4 0x10 +#define LED5 0x20 +#define LED6 0x40 +#define LED7 0x80 +//! @} + + +/*! \brief Gets the last state of all LEDs set through the LED API. + * + * \return State of all LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display(void); + +/*! \brief Sets the state of all LEDs. + * + * \param leds New state of all LEDs (1 bit per LED). + * + * \note The pins of all LEDs are set to GPIO output mode. + */ +extern void LED_Display(U32 leds); + +/*! \brief Gets the last state of the specified LEDs set through the LED API. + * + * \param mask LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Mask(U32 mask); + +/*! \brief Sets the state of the specified LEDs. + * + * \param mask LEDs of which to set the state (1 bit per LED). + * + * \param leds New state of the specified LEDs (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Mask(U32 mask, U32 leds); + +/*! \brief Tests the last state of the specified LEDs set through the LED API. + * + * \param leds LEDs of which to test the state (1 bit per LED). + * + * \return \c TRUE if at least one of the specified LEDs has a state on, else + * \c FALSE. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern Bool LED_Test(U32 leds); + +/*! \brief Turns off the specified LEDs. + * + * \param leds LEDs to turn off (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Off(U32 leds); + +/*! \brief Turns on the specified LEDs. + * + * \param leds LEDs to turn on (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_On(U32 leds); + +/*! \brief Toggles the specified LEDs. + * + * \param leds LEDs to toggle (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Toggle(U32 leds); + +/*! \brief Gets as a bit-field the last state of the specified LEDs set through + * the LED API. + * + * \param field LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED, beginning with the first + * specified LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Field(U32 field); + +/*! \brief Sets as a bit-field the state of the specified LEDs. + * + * \param field LEDs of which to set the state (1 bit per LED). + * \param leds New state of the specified LEDs (1 bit per LED, beginning with + * the first specified LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Field(U32 field, U32 leds); + +/*! \brief Gets the intensity of the specified LED. + * + * \param led LED of which to get the intensity (1 bit per LED; only the least + * significant set bit is used). + * + * \return Intensity of the specified LED (0x00 to 0xFF). + * + * \warning The PWM channel of the specified LED is supposed to be used only by + * this module. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U8 LED_Get_Intensity(U32 led); + +/*! \brief Sets the intensity of the specified LEDs. + * + * \param leds LEDs of which to set the intensity (1 bit per LED). + * \param intensity New intensity of the specified LEDs (0x00 to 0xFF). + * + * \warning The PWM channels of the specified LEDs are supposed to be used only + * by this module. + * + * \note The pins of the specified LEDs are set to PWM output mode. + */ +extern void LED_Set_Intensity(U32 leds, U8 intensity); + + +#endif // _LED_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/EVK1105/evk1105.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/EVK1105/evk1105.h new file mode 100644 index 0000000..edda44c --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/EVK1105/evk1105.h @@ -0,0 +1,433 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1105 board header file. + * + * This file contains definitions and services related to the features of the + * EVK1105 board rev. B. + * + * To use this board, define BOARD=EVK1105. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _EVK1105_H_ +#define _EVK1105_H_ + +#ifdef EVK1105_REV3 +# include "evk1105_rev3.h" +#else + +#include "compiler.h" + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. +# include "led.h" +#endif // __AVR32_ABI_COMPILER__ + + +/*! \name Oscillator Definitions + */ +//! @{ + +// RCOsc has no custom calibration by default. Set the following definition to +// the appropriate value if a custom RCOsc calibration has been applied to your +// part. +//#define FRCOSC AVR32_PM_RCOSC_FREQUENCY //!< RCOsc frequency: Hz. + +#define FOSC32 32768 //!< Osc32 frequency: Hz. +#define OSC32_STARTUP AVR32_PM_OSCCTRL32_STARTUP_8192_RCOSC //!< Osc32 startup time: RCOsc periods. + +#define FOSC0 12000000 //!< Osc0 frequency: Hz. +#define OSC0_STARTUP AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC //!< Osc0 startup time: RCOsc periods. + +#define FOSC1 11289600 //!< Osc1 frequency: Hz +#define OSC1_STARTUP AVR32_PM_OSCCTRL1_STARTUP_2048_RCOSC //!< Osc1 startup time: RCOsc periods. + + +//! @} + + +/*! \name SDRAM Definitions + */ +//! @{ + +//! Part header file of used SDRAM(s). +#define SDRAM_PART_HDR "MT48LC16M16A2TG7E/mt48lc16m16a2tg7e.h" + +//! Data bus width to use the SDRAM(s) with (16 or 32 bits; always 16 bits on +//! UC3). +#define SDRAM_DBW 16 +//! @} + + +/*! \name USB Definitions + */ +//! @{ +//! Multiplexed pin used for USB_ID: AVR32_USBB_USB_ID_x_x. +//! To be selected according to the AVR32_USBB_USB_ID_x_x_PIN and +//! AVR32_USBB_USB_ID_x_x_FUNCTION definitions from <avr32/uc3axxxx.h>. +#define AVR32_USBB_USB_ID_0_2_PIN 21 +#define AVR32_USBB_USB_ID_0_2_FUNCTION 2 +#define USB_ID AVR32_USBB_USB_ID_0_2 + +//! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x. +//! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and +//! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from <avr32/uc3axxxx.h>. +# define USB_VBOF AVR32_USBB_USB_VBOF_0_1 + + +//! Active level of the USB_VBOF output pin. +# define USB_VBOF_ACTIVE_LEVEL LOW + +//! USB overcurrent detection pin. +# define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PX15 + +//! @} + + +//! GPIO connection of the MAC PHY PWR_DOWN/INT signal. +# define MACB_INTERRUPT_PIN AVR32_PIN_PA26 + + + +//! Number of LEDs. +#define LED_COUNT 4 + +/*! \name GPIO Connections of LEDs + */ +//! @{ +# define LED0_GPIO AVR32_PIN_PB27 +# define LED1_GPIO AVR32_PIN_PB28 +# define LED2_GPIO AVR32_PIN_PA05 +# define LED3_GPIO AVR32_PIN_PA06 +//! @} + +/*! \name Color Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#define LED_MONO0_GREEN LED0 +#define LED_MONO1_GREEN LED1 +#define LED_MONO2_GREEN LED2 +#define LED_MONO3_GREEN LED3 +//! @} + +/*! \name PWM Channels of LEDs + */ +//! @{ +#define LED0_PWM 4 +#define LED1_PWM 5 +#define LED2_PWM (-1) +#define LED3_PWM (-1) +//! @} + +/*! \name PWM Functions of LEDs + */ +//! @{ +/* TODO: Implement PWM functionality */ +#define LED0_PWM_FUNCTION (-1)//AVR32_PWM_0_FUNCTION +#define LED1_PWM_FUNCTION (-1)//AVR32_PWM_1_FUNCTION +#define LED2_PWM_FUNCTION (-1) +#define LED3_PWM_FUNCTION (-1) +//! @} + +//! External interrupt connection of touch sensor. +#define QT1081_EIC_EXTINT_PIN AVR32_EIC_EXTINT_1_PIN +#define QT1081_EIC_EXTINT_FUNCTION AVR32_EIC_EXTINT_1_FUNCTION +#define QT1081_EIC_EXTINT_IRQ AVR32_EIC_IRQ_1 +#define QT1081_EIC_EXTINT_INT AVR32_EIC_INT1 +/*! \name Touch sensor low power mode select + */ +#define QT1081_LP_MODE AVR32_PIN_PB29 + +/*! \name GPIO Connections of touch buttons + */ +//! @{ +#define QT1081_TOUCH_SENSOR_0 AVR32_PIN_PB22 +#define QT1081_TOUCH_SENSOR_0_PRESSED 1 +#define QT1081_TOUCH_SENSOR_1 AVR32_PIN_PB23 +#define QT1081_TOUCH_SENSOR_1_PRESSED 1 +#define QT1081_TOUCH_SENSOR_2 AVR32_PIN_PB24 +#define QT1081_TOUCH_SENSOR_2_PRESSED 1 +#define QT1081_TOUCH_SENSOR_3 AVR32_PIN_PB25 +#define QT1081_TOUCH_SENSOR_3_PRESSED 1 +#define QT1081_TOUCH_SENSOR_4 AVR32_PIN_PB26 +#define QT1081_TOUCH_SENSOR_4_PRESSED 1 + +#define QT1081_TOUCH_SENSOR_ENTER QT1081_TOUCH_SENSOR_4 +#define QT1081_TOUCH_SENSOR_ENTER_PRESSED QT1081_TOUCH_SENSOR_4_PRESSED +#define QT1081_TOUCH_SENSOR_LEFT QT1081_TOUCH_SENSOR_3 +#define QT1081_TOUCH_SENSOR_LEFT_PRESSED QT1081_TOUCH_SENSOR_3_PRESSED +#define QT1081_TOUCH_SENSOR_RIGHT QT1081_TOUCH_SENSOR_2 +#define QT1081_TOUCH_SENSOR_RIGHT_PRESSED QT1081_TOUCH_SENSOR_2_PRESSED +#define QT1081_TOUCH_SENSOR_UP QT1081_TOUCH_SENSOR_0 +#define QT1081_TOUCH_SENSOR_UP_PRESSED QT1081_TOUCH_SENSOR_0_PRESSED +#define QT1081_TOUCH_SENSOR_DOWN QT1081_TOUCH_SENSOR_1 +#define QT1081_TOUCH_SENSOR_DOWN_PRESSED QT1081_TOUCH_SENSOR_1_PRESSED +//! @} + +/*! \name SPI Connections of the AT45DBX Data Flash Memory + */ +//! @{ +#define AT45DBX_SPI (&AVR32_SPI0) +#define AT45DBX_SPI_NPCS 0 +#define AT45DBX_SPI_SCK_PIN AVR32_SPI0_SCK_0_0_PIN +#define AT45DBX_SPI_SCK_FUNCTION AVR32_SPI0_SCK_0_0_FUNCTION +#define AT45DBX_SPI_MISO_PIN AVR32_SPI0_MISO_0_0_PIN +#define AT45DBX_SPI_MISO_FUNCTION AVR32_SPI0_MISO_0_0_FUNCTION +#define AT45DBX_SPI_MOSI_PIN AVR32_SPI0_MOSI_0_0_PIN +#define AT45DBX_SPI_MOSI_FUNCTION AVR32_SPI0_MOSI_0_0_FUNCTION +#define AT45DBX_SPI_NPCS0_PIN AVR32_SPI0_NPCS_0_0_PIN +#define AT45DBX_SPI_NPCS0_FUNCTION AVR32_SPI0_NPCS_0_0_FUNCTION +//! @} + +/*! \name GPIO and SPI Connections of the SD/MMC Connector + */ +//! @{ +#define SD_MMC_CARD_DETECT_PIN AVR32_PIN_PA02 +#define SD_MMC_WRITE_PROTECT_PIN AVR32_PIN_PA18 +#define SD_MMC_SPI (&AVR32_SPI0) +#define SD_MMC_SPI_NPCS 1 +#define SD_MMC_SPI_SCK_PIN AVR32_SPI0_SCK_0_0_PIN +#define SD_MMC_SPI_SCK_FUNCTION AVR32_SPI0_SCK_0_0_FUNCTION +#define SD_MMC_SPI_MISO_PIN AVR32_SPI0_MISO_0_0_PIN +#define SD_MMC_SPI_MISO_FUNCTION AVR32_SPI0_MISO_0_0_FUNCTION +#define SD_MMC_SPI_MOSI_PIN AVR32_SPI0_MOSI_0_0_PIN +#define SD_MMC_SPI_MOSI_FUNCTION AVR32_SPI0_MOSI_0_0_FUNCTION +#define SD_MMC_SPI_NPCS_PIN AVR32_SPI0_NPCS_1_0_PIN +#define SD_MMC_SPI_NPCS_FUNCTION AVR32_SPI0_NPCS_1_0_FUNCTION +//! @} + + +/*! \name TWI expansion + */ +//! @{ +#define EXPANSION_TWI (&AVR32_TWI) +#define EXPANSION_RESET AVR32_PIN_PX16 +#define EXPANSION_TWI_SCL_PIN AVR32_TWI_SCL_0_0_PIN +#define EXPANSION_TWI_SCL_FUNCTION AVR32_TWI_SCL_0_0_FUNCTION +#define EXPANSION_TWI_SDA_PIN AVR32_TWI_SDA_0_0_PIN +#define EXPANSION_TWI_SDA_FUNCTION AVR32_TWI_SDA_0_0_FUNCTION +//! @} + +/*! \name Wireless expansion + */ + +#define WEXPANSION_EXTINT_PIN AVR32_EIC_EXTINT_8_PIN +#define WEXPANSION_EXTINT_FUNCTION AVR32_EIC_EXTINT_8_FUNCTION +#define WEXPANSION_GPIO1 AVR32_PIN_PB30 +#define WEXPANSION_GPIO2 AVR32_PIN_PB31 + +#define WEXPANSION_SPI (&AVR32_SPI0) +#define WEXPANSION_SPI_NPCS 2 +#define WEXPANSION_SPI_SCK_PIN AVR32_SPI0_SCK_0_0_PIN +#define WEXPANSION_SPI_SCK_FUNCTION AVR32_SPI0_SCK_0_0_FUNCTION +#define WEXPANSION_SPI_MISO_PIN AVR32_SPI0_MISO_0_0_PIN +#define WEXPANSION_SPI_MISO_FUNCTION AVR32_SPI0_MISO_0_0_FUNCTION +#define WEXPANSION_SPI_MOSI_PIN AVR32_SPI0_MOSI_0_0_PIN +#define WEXPANSION_SPI_MOSI_FUNCTION AVR32_SPI0_MOSI_0_0_FUNCTION +#define WEXPANSION_SPI_NPCS_PIN AVR32_SPI0_NPCS_2_0_PIN +#define WEXPANSION_SPI_NPCS_FUNCTION AVR32_SPI0_NPCS_2_0_FUNCTION + +//! @} + +/*! \name ET024006DHU TFT display + */ +//! @{ + +#define ET024006DHU_TE_PIN AVR32_PIN_PX19 +#define ET024006DHU_RESET_PIN AVR32_PIN_PX22 +#define ET024006DHU_BL_PIN AVR32_PWM_6_PIN +#define ET024006DHU_BL_FUNCTION AVR32_PWM_6_FUNCTION +#define ET024006DHU_DNC_PIN AVR32_EBI_ADDR_21_1_PIN +#define ET024006DHU_DNC_FUNCTION AVR32_EBI_ADDR_21_1_FUNCTION +#define ET024006DHU_EBI_NCS_PIN AVR32_EBI_NCS_0_1_PIN +#define ET024006DHU_EBI_NCS_FUNCTION AVR32_EBI_NCS_0_1_FUNCTION + +//! @} +/*! \name Optional SPI connection to the TFT + */ +//! @{ + +#define ET024006DHU_SPI (&AVR32_SPI0) +#define ET024006DHU_SPI_NPCS 3 +#define ET024006DHU_SPI_SCK_PIN AVR32_SPI0_SCK_0_0_PIN +#define ET024006DHU_SPI_SCK_FUNCTION AVR32_SPI0_SCK_0_0_FUNCTION +#define ET024006DHU_SPI_MISO_PIN AVR32_SPI0_MISO_0_0_PIN +#define ET024006DHU_SPI_MISO_FUNCTION AVR32_SPI0_MISO_0_0_FUNCTION +#define ET024006DHU_SPI_MOSI_PIN AVR32_SPI0_MOSI_0_0_PIN +#define ET024006DHU_SPI_MOSI_FUNCTION AVR32_SPI0_MOSI_0_0_FUNCTION +#define ET024006DHU_SPI_NPCS_PIN AVR32_SPI1_NPCS_3_0_PIN +#define ET024006DHU_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_3_0_FUNCTION + +//! @} + + +/*! \name Audio amplifier connection to the DAC + */ +//! @{ + +#define TPA6130_ABDAC (&AVR32_ABDAC) + +#define TPA6130_DATA0_PIN AVR32_ABDAC_DATA_0_1_PIN +#define TPA6130_DATA0_FUNCTION AVR32_ABDAC_DATA_0_1_FUNCTION +#define TPA6130_DATAN0_PIN AVR32_ABDAC_DATAN_0_1_PIN +#define TPA6130_DATAN0_FUNCTION AVR32_ABDAC_DATAN_0_1_FUNCTION +#define TPA6130_DATA1_PIN AVR32_ABDAC_DATA_1_1_PIN +#define TPA6130_DATA1_FUNCTION AVR32_ABDAC_DATA_1_1_FUNCTION +#define TPA6130_DATAN1_PIN AVR32_ABDAC_DATAN_1_1_PIN +#define TPA6130_DATAN1_FUNCTION AVR32_ABDAC_DATAN_1_1_FUNCTION + +#define TPA6130_ABDAC_PDCA_PID AVR32_PDCA_PID_ABDAC_TX +#define TPA6130_ABDAC_PDCA_CHANNEL 0 +#define TPA6130_ABDAC_PDCA_IRQ AVR32_PDCA_IRQ_0 +#define TPA6130_ABDAC_PDCA_INT_LEVEL AVR32_INTC_INT3 + +#define TPA6130_TWI (&AVR32_TWI) +#define TPA6130_TWI_SCL_PIN AVR32_TWI_SCL_0_0_PIN +#define TPA6130_TWI_SCL_FUNCTION AVR32_TWI_SCL_0_0_FUNCTION +#define TPA6130_TWI_SDA_PIN AVR32_TWI_SDA_0_0_PIN +#define TPA6130_TWI_SDA_FUNCTION AVR32_TWI_SDA_0_0_FUNCTION + +//! }@ +/*! \name TI TLV320AIC23B sound chip + */ +//! @{ +#define TLV320_SSC (&AVR32_SSC) +#define TLV320_SSC_TX_CLOCK_PIN AVR32_SSC_TX_CLOCK_0_PIN +#define TLV320_SSC_TX_CLOCK_FUNCTION AVR32_SSC_TX_CLOCK_0_FUNCTION +#define TLV320_SSC_TX_DATA_PIN AVR32_SSC_TX_DATA_0_PIN +#define TLV320_SSC_TX_DATA_FUNCTION AVR32_SSC_TX_DATA_0_FUNCTION +#define TLV320_SSC_TX_FRAME_SYNC_PIN AVR32_SSC_TX_FRAME_SYNC_0_PIN +#define TLV320_SSC_TX_FRAME_SYNC_FUNCTION AVR32_SSC_TX_FRAME_SYNC_0_FUNCTION + +#define TLV320_TWI (&AVR32_TWI) +#define TLV320_TWI_SCL_PIN AVR32_TWI_SCL_0_0_PIN +#define TLV320_TWI_SCL_FUNCTION AVR32_TWI_SCL_0_0_FUNCTION +#define TLV320_TWI_SDA_PIN AVR32_TWI_SDA_0_0_PIN +#define TLV320_TWI_SDA_FUNCTION AVR32_TWI_SDA_0_0_FUNCTION + +#define TLV320_PM_GCLK_PIN AVR32_PM_GCLK_0_0_PIN +#define TLV320_PM_GCLK_FUNCTION AVR32_PM_GCLK_0_0_FUNCTION +//! @} + +////! \name SPI: Apple Authentication Chip Hardware Connections +////! @{ +#define IPOD_AUTH_CHIP_SPI (&AVR32_SPI0) +#define IPOD_AUTH_CHIP_SPI_IRQ AVR32_SPI0_IRQ +#define IPOD_AUTH_CHIP_SPI_NPCS 2 +#define IPOD_AUTH_CHIP_SPI_SCK_PIN AVR32_SPI0_SCK_0_0_PIN +#define IPOD_AUTH_CHIP_SPI_SCK_FUNCTION AVR32_SPI0_SCK_0_0_FUNCTION +#define IPOD_AUTH_CHIP_SPI_MISO_PIN AVR32_SPI0_MISO_0_0_PIN +#define IPOD_AUTH_CHIP_SPI_MISO_FUNCTION AVR32_SPI0_MISO_0_0_FUNCTION +#define IPOD_AUTH_CHIP_SPI_MOSI_PIN AVR32_SPI0_MOSI_0_0_PIN +#define IPOD_AUTH_CHIP_SPI_MOSI_FUNCTION AVR32_SPI0_MOSI_0_0_FUNCTION +#define IPOD_AUTH_CHIP_SPI_NPCS_PIN AVR32_SPI0_NPCS_2_0_PIN +#define IPOD_AUTH_CHIP_SPI_NPCS_FUNCTION AVR32_SPI0_NPCS_2_0_FUNCTION +#define IPOD_AUTH_CHIP_SPI_N_RESET_PIN AVR32_PIN_PB30 +#define IPOD_AUTH_CHIP_SPI_CP_READY_PIN AVR32_PIN_PB31 +//! }@ + +/*! \name Connections of the iPOD Authentication Coprocessor + */ +//! @{ + +#define IPOD_AUTH_CHIP_TWI (&AVR32_TWI) +#define IPOD_AUTH_CHIP_TWI_SCL_PIN AVR32_TWI_SCL_0_0_PIN +#define IPOD_AUTH_CHIP_TWI_SCL_FUNCTION AVR32_TWI_SCL_0_0_FUNCTION +#define IPOD_AUTH_CHIP_TWI_SDA_PIN AVR32_TWI_SDA_0_0_PIN +#define IPOD_AUTH_CHIP_TWI_SDA_FUNCTION AVR32_TWI_SDA_0_0_FUNCTION +#define IPOD_AUTH_CHIP_TWI_N_RESET_PIN AVR32_PIN_PX16 + +//! @} + +/*! \name USART connection to the UC3B board controller + */ +//! @{ + +#define USART0_RXD_PIN AVR32_USART0_RXD_0_0_PIN +#define USART0_RXD_FUNCTION AVR32_USART0_RXD_0_0_FUNCTION +#define USART0_TXD_PIN AVR32_USART0_TXD_0_0_PIN +#define USART0_TXD_FUNCTION AVR32_USART0_TXD_0_0_FUNCTION +#define USART0_RTS_PIN AVR32_USART0_RTS_0_0_PIN +#define USART0_RTS_FUNCTION AVR32_USART0_RTS_0_0_FUNCTION +#define USART0_CTS_PIN AVR32_USART0_CTS_0_0_PIN +#define USART0_CTS_FUNCTION AVR32_USART0_CTS_0_0_FUNCTION + +//! @} + +#define ADC_VEXT_PIN AVR32_ADC_AD_7_PIN +#define ADC_VEXT_FUNCTION AVR32_ADC_AD_7_FUNCTION + +/*! \name LCD Connections of the ET024006DHU display + */ +//! @{ +#define ET024006DHU_SMC_USE_NCS 0 +#define ET024006DHU_SMC_COMPONENT_CS "smc_et024006dhu.h" + +#define ET024006DHU_EBI_DATA_0 AVR32_EBI_DATA_0 +#define ET024006DHU_EBI_DATA_1 AVR32_EBI_DATA_1 +#define ET024006DHU_EBI_DATA_2 AVR32_EBI_DATA_2 +#define ET024006DHU_EBI_DATA_3 AVR32_EBI_DATA_3 +#define ET024006DHU_EBI_DATA_4 AVR32_EBI_DATA_4 +#define ET024006DHU_EBI_DATA_5 AVR32_EBI_DATA_5 +#define ET024006DHU_EBI_DATA_6 AVR32_EBI_DATA_6 +#define ET024006DHU_EBI_DATA_7 AVR32_EBI_DATA_7 +#define ET024006DHU_EBI_DATA_8 AVR32_EBI_DATA_8 +#define ET024006DHU_EBI_DATA_9 AVR32_EBI_DATA_9 +#define ET024006DHU_EBI_DATA_10 AVR32_EBI_DATA_10 +#define ET024006DHU_EBI_DATA_11 AVR32_EBI_DATA_11 +#define ET024006DHU_EBI_DATA_12 AVR32_EBI_DATA_12 +#define ET024006DHU_EBI_DATA_13 AVR32_EBI_DATA_13 +#define ET024006DHU_EBI_DATA_14 AVR32_EBI_DATA_14 +#define ET024006DHU_EBI_DATA_15 AVR32_EBI_DATA_15 + +#define ET024006DHU_EBI_ADDR_21 AVR32_EBI_ADDR_21_1 + +#define ET024006DHU_EBI_NWE AVR32_EBI_NWE0_0 +#define ET024006DHU_EBI_NRD AVR32_EBI_NRD_0 +#define ET024006DHU_EBI_NCS AVR32_EBI_NCS_0_1 +//! @} + + +#endif // !EVK1105_REVA + +#endif // _EVK1105_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/EVK1105/led.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/EVK1105/led.c new file mode 100644 index 0000000..561652a --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/EVK1105/led.c @@ -0,0 +1,346 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1105 board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the EVK1105 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include <avr32/io.h> +#include "preprocessor.h" +#include "compiler.h" +#include "evk1105.h" +#include "led.h" + + +//! Structure describing LED hardware connections. +typedef const struct +{ + struct + { + U32 PORT; //!< LED GPIO port. + U32 PIN_MASK; //!< Bit-mask of LED pin in GPIO port. + } GPIO; //!< LED GPIO descriptor. + struct + { + S32 CHANNEL; //!< LED PWM channel (< 0 if N/A). + S32 FUNCTION; //!< LED pin PWM function (< 0 if N/A). + } PWM; //!< LED PWM descriptor. +} tLED_DESCRIPTOR; + + +//! Hardware descriptors of all LEDs. +static tLED_DESCRIPTOR LED_DESCRIPTOR[LED_COUNT] = +{ +#define INSERT_LED_DESCRIPTOR(LED_NO, unused) \ + { \ + {LED##LED_NO##_GPIO / 32, 1 << (LED##LED_NO##_GPIO % 32)},\ + {LED##LED_NO##_PWM, LED##LED_NO##_PWM_FUNCTION } \ + }, + MREPEAT(LED_COUNT, INSERT_LED_DESCRIPTOR, ~) +#undef INSERT_LED_DESCRIPTOR +}; + + +//! Saved state of all LEDs. +static volatile U32 LED_State = (1 << LED_COUNT) - 1; + + +U32 LED_Read_Display(void) +{ + return LED_State; +} + + +void LED_Display(U32 leds) +{ + // Use the LED descriptors to get the connections of a given LED to the MCU. + tLED_DESCRIPTOR *led_descriptor; + volatile avr32_gpio_port_t *led_gpio_port; + + // Make sure only existing LEDs are specified. + leds &= (1 << LED_COUNT) - 1; + + // Update the saved state of all LEDs with the requested changes. + LED_State = leds; + + // For all LEDs... + for (led_descriptor = &LED_DESCRIPTOR[0]; + led_descriptor < LED_DESCRIPTOR + LED_COUNT; + led_descriptor++) + { + // Set the LED to the requested state. + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + if (leds & 1) + { + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= 1; + } +} + + +U32 LED_Read_Display_Mask(U32 mask) +{ + return Rd_bits(LED_State, mask); +} + + +void LED_Display_Mask(U32 mask, U32 leds) +{ + // Use the LED descriptors to get the connections of a given LED to the MCU. + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // Make sure only existing LEDs are specified. + mask &= (1 << LED_COUNT) - 1; + + // Update the saved state of all LEDs with the requested changes. + Wr_bits(LED_State, mask, leds); + + // While there are specified LEDs left to manage... + while (mask) + { + // Select the next specified LED and set it to the requested state. + led_shift = 1 + ctz(mask); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + leds >>= led_shift - 1; + if (leds & 1) + { + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= 1; + mask >>= led_shift; + } +} + + +Bool LED_Test(U32 leds) +{ + return Tst_bits(LED_State, leds); +} + + +void LED_Off(U32 leds) +{ + // Use the LED descriptors to get the connections of a given LED to the MCU. + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // Make sure only existing LEDs are specified. + leds &= (1 << LED_COUNT) - 1; + + // Update the saved state of all LEDs with the requested changes. + Clr_bits(LED_State, leds); + + // While there are specified LEDs left to manage... + while (leds) + { + // Select the next specified LED and turn it off. + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +void LED_On(U32 leds) +{ + // Use the LED descriptors to get the connections of a given LED to the MCU. + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // Make sure only existing LEDs are specified. + leds &= (1 << LED_COUNT) - 1; + + // Update the saved state of all LEDs with the requested changes. + Set_bits(LED_State, leds); + + // While there are specified LEDs left to manage... + while (leds) + { + // Select the next specified LED and turn it on. + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +void LED_Toggle(U32 leds) +{ + // Use the LED descriptors to get the connections of a given LED to the MCU. + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // Make sure only existing LEDs are specified. + leds &= (1 << LED_COUNT) - 1; + + // Update the saved state of all LEDs with the requested changes. + Tgl_bits(LED_State, leds); + + // While there are specified LEDs left to manage... + while (leds) + { + // Select the next specified LED and toggle it. + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrt = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +U32 LED_Read_Display_Field(U32 field) +{ + return Rd_bitfield(LED_State, field); +} + + +void LED_Display_Field(U32 field, U32 leds) +{ + // Move the bit-field to the appropriate position for the bit-mask. + LED_Display_Mask(field, leds << ctz(field)); +} + + +U8 LED_Get_Intensity(U32 led) +{ + tLED_DESCRIPTOR *led_descriptor; + + // Check that the argument value is valid. + led = ctz(led); + led_descriptor = &LED_DESCRIPTOR[led]; + if (led >= LED_COUNT || led_descriptor->PWM.CHANNEL < 0) return 0; + + // Return the duty cycle value if the LED PWM channel is enabled, else 0. + return (AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)) ? + AVR32_PWM.channel[led_descriptor->PWM.CHANNEL].cdty : 0; +} + + +void LED_Set_Intensity(U32 leds, U8 intensity) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_pwm_channel_t *led_pwm_channel; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // For each specified LED... + for (leds &= (1 << LED_COUNT) - 1; leds; leds >>= led_shift) + { + // Select the next specified LED and check that it has a PWM channel. + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + if (led_descriptor->PWM.CHANNEL < 0) continue; + + // Initialize or update the LED PWM channel. + led_pwm_channel = &AVR32_PWM.channel[led_descriptor->PWM.CHANNEL]; + if (!(AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL))) + { + led_pwm_channel->cmr = (AVR32_PWM_CPRE_MCK << AVR32_PWM_CPRE_OFFSET) & + ~(AVR32_PWM_CALG_MASK | + AVR32_PWM_CPOL_MASK | + AVR32_PWM_CPD_MASK); + led_pwm_channel->cprd = 0x000000FF; + led_pwm_channel->cdty = intensity; + AVR32_PWM.ena = 1 << led_descriptor->PWM.CHANNEL; + } + else + { + AVR32_PWM.isr; + while (!(AVR32_PWM.isr & (1 << led_descriptor->PWM.CHANNEL))); + led_pwm_channel->cupd = intensity; + } + + // Switch the LED pin to its PWM function. + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + if (led_descriptor->PWM.FUNCTION & 0x1) + { + led_gpio_port->pmr0s = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->pmr0c = led_descriptor->GPIO.PIN_MASK; + } + if (led_descriptor->PWM.FUNCTION & 0x2) + { + led_gpio_port->pmr1s = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->pmr1c = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->gperc = led_descriptor->GPIO.PIN_MASK; + } +} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/EVK1105/led.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/EVK1105/led.h new file mode 100644 index 0000000..7766b6a --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/EVK1105/led.h @@ -0,0 +1,187 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1105 board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the EVK1105 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _LED_H_ +#define _LED_H_ + +#include "compiler.h" + + +/*! \name Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#define LED0 0x01 +#define LED1 0x02 +#define LED2 0x04 +#define LED3 0x08 +//! @} + + +/*! \brief Gets the last state of all LEDs set through the LED API. + * + * \return State of all LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display(void); + +/*! \brief Sets the state of all LEDs. + * + * \param leds New state of all LEDs (1 bit per LED). + * + * \note The pins of all LEDs are set to GPIO output mode. + */ +extern void LED_Display(U32 leds); + +/*! \brief Gets the last state of the specified LEDs set through the LED API. + * + * \param mask LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Mask(U32 mask); + +/*! \brief Sets the state of the specified LEDs. + * + * \param mask LEDs of which to set the state (1 bit per LED). + * + * \param leds New state of the specified LEDs (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Mask(U32 mask, U32 leds); + +/*! \brief Tests the last state of the specified LEDs set through the LED API. + * + * \param leds LEDs of which to test the state (1 bit per LED). + * + * \return \c TRUE if at least one of the specified LEDs has a state on, else + * \c FALSE. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern Bool LED_Test(U32 leds); + +/*! \brief Turns off the specified LEDs. + * + * \param leds LEDs to turn off (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Off(U32 leds); + +/*! \brief Turns on the specified LEDs. + * + * \param leds LEDs to turn on (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_On(U32 leds); + +/*! \brief Toggles the specified LEDs. + * + * \param leds LEDs to toggle (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Toggle(U32 leds); + +/*! \brief Gets as a bit-field the last state of the specified LEDs set through + * the LED API. + * + * \param field LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED, beginning with the first + * specified LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Field(U32 field); + +/*! \brief Sets as a bit-field the state of the specified LEDs. + * + * \param field LEDs of which to set the state (1 bit per LED). + * \param leds New state of the specified LEDs (1 bit per LED, beginning with + * the first specified LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Field(U32 field, U32 leds); + +/*! \brief Gets the intensity of the specified LED. + * + * \param led LED of which to get the intensity (1 bit per LED; only the least + * significant set bit is used). + * + * \return Intensity of the specified LED (0x00 to 0xFF). + * + * \warning The PWM channel of the specified LED is supposed to be used only by + * this module. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U8 LED_Get_Intensity(U32 led); + +/*! \brief Sets the intensity of the specified LEDs. + * + * \param leds LEDs of which to set the intensity (1 bit per LED). + * \param intensity New intensity of the specified LEDs (0x00 to 0xFF). + * + * \warning The PWM channels of the specified LEDs are supposed to be used only + * by this module. + * + * \note The pins of the specified LEDs are set to PWM output mode. + */ +extern void LED_Set_Intensity(U32 leds, U8 intensity); + + +#endif // _LED_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/board.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/board.h new file mode 100644 index 0000000..78ee91e --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/board.h @@ -0,0 +1,120 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Standard board header file. + * + * This file includes the appropriate board header file according to the + * defined board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include <avr32/io.h> + +/*! \name Base Boards + */ +//! @{ +#define EVK1100 1 //!< AT32UC3A EVK1100 board. +#define EVK1101 2 //!< AT32UC3B EVK1101 board. +#define UC3C_EK 3 //!< AT32UC3C UC3C_EK board. +#define EVK1104 4 //!< AT32UC3A3 EVK1104 board. +#define EVK1105 5 //!< AT32UC3A EVK1105 board. +#define STK1000 6 //!< AT32AP7000 STK1000 board. +#define NGW100 7 //!< AT32AP7000 NGW100 board. +#define STK600_RCUC3L0 8 //!< STK600 RCUC3L0 board. +#define UC3L_EK 9 //!< AT32UC3L-EK board. +#define USER_BOARD 99 //!< User-reserved board (if any). +//! @} + +/*! \name Extension Boards + */ +//! @{ +#define EXT1102 1 //!< AT32UC3B EXT1102 board. +#define MC300 2 //!< AT32UC3 MC300 board. +#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any). +//! @} + +#if BOARD == EVK1100 + #include "EVK1100/evk1100.h" +#elif BOARD == EVK1101 + #include "EVK1101/evk1101.h" +#elif BOARD == UC3C_EK + #include "UC3C_EK/uc3c_ek.h" +#elif BOARD == EVK1104 + #include "EVK1104/evk1104.h" +#elif BOARD == EVK1105 + #include "EVK1105/evk1105.h" +#elif BOARD == STK1000 + #include "STK1000/stk1000.h" +#elif BOARD == NGW100 + #include "NGW100/ngw100.h" +#elif BOARD == STK600_RCUC3L0 + #include "STK600/RCUC3L0/stk600_rcuc3l0.h" +#elif BOARD == UC3L_EK + #include "UC3L_EK/uc3l_ek.h" +#elif BOARD == ARDUINO + #include "ARDUINO/arduino.h" +#else + #error No known AVR32 board defined +#endif + +#if (defined EXT_BOARD) + #if EXT_BOARD == EXT1102 + #include "EXT1102/ext1102.h" + #elif EXT_BOARD == MC300 + #include "MC300/mc300.h" + #elif EXT_BOARD == USER_EXT_BOARD + // User-reserved area: #include the header file of your extension board here + // (if any). + #endif +#endif + + +#ifndef FRCOSC + #define FRCOSC AVR32_PM_RCOSC_FREQUENCY //!< Default RCOsc frequency. +#endif + + +#endif // _BOARD_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/board.h.ori b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/board.h.ori new file mode 100644 index 0000000..30052c8 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/BOARDS/board.h.ori @@ -0,0 +1,121 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Standard board header file. + * + * This file includes the appropriate board header file according to the + * defined board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include <avr32/io.h> + +/*! \name Base Boards + */ +//! @{ +#define EVK1100 1 //!< AT32UC3A EVK1100 board. +#define EVK1101 2 //!< AT32UC3B EVK1101 board. +#define UC3C_EK 3 //!< AT32UC3C UC3C_EK board. +#define EVK1104 4 //!< AT32UC3A3 EVK1104 board. +#define EVK1105 5 //!< AT32UC3A EVK1105 board. +#define STK1000 6 //!< AT32AP7000 STK1000 board. +#define NGW100 7 //!< AT32AP7000 NGW100 board. +#define STK600_RCUC3L0 8 //!< STK600 RCUC3L0 board. +#define UC3L_EK 9 //!< AT32UC3L-EK board. +#define USER_BOARD 99 //!< User-reserved board (if any). +//! @} + +/*! \name Extension Boards + */ +//! @{ +#define EXT1102 1 //!< AT32UC3B EXT1102 board. +#define MC300 2 //!< AT32UC3 MC300 board. +#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any). +//! @} + +#if BOARD == EVK1100 + #include "EVK1100/evk1100.h" +#elif BOARD == EVK1101 + #include "EVK1101/evk1101.h" +#elif BOARD == UC3C_EK + #include "UC3C_EK/uc3c_ek.h" +#elif BOARD == EVK1104 + #include "EVK1104/evk1104.h" +#elif BOARD == EVK1105 + #include "EVK1105/evk1105.h" +#elif BOARD == STK1000 + #include "STK1000/stk1000.h" +#elif BOARD == NGW100 + #include "NGW100/ngw100.h" +#elif BOARD == STK600_RCUC3L0 + #include "STK600/RCUC3L0/stk600_rcuc3l0.h" +#elif BOARD == UC3L_EK + #include "UC3L_EK/uc3l_ek.h" +#elif BOARD == USER_BOARD + // User-reserved area: #include the header file of your board here (if any). + #include "user_board.h" +#else + #error No known AVR32 board defined +#endif + +#if (defined EXT_BOARD) + #if EXT_BOARD == EXT1102 + #include "EXT1102/ext1102.h" + #elif EXT_BOARD == MC300 + #include "MC300/mc300.h" + #elif EXT_BOARD == USER_EXT_BOARD + // User-reserved area: #include the header file of your extension board here + // (if any). + #endif +#endif + + +#ifndef FRCOSC + #define FRCOSC AVR32_PM_RCOSC_FREQUENCY //!< Default RCOsc frequency. +#endif + + +#endif // _BOARD_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx.c new file mode 100644 index 0000000..d4b1b73 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx.c @@ -0,0 +1,672 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Management of the AT45DBX data flash controller through SPI. + * + * This file manages the accesses to the AT45DBX data flash components. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an SPI module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +//_____ I N C L U D E S ___________________________________________________ + +#include "conf_access.h" + + +#if AT45DBX_MEM == ENABLE + +#include "compiler.h" +#include "board.h" +#include "gpio.h" +#include "spi.h" +#include "conf_at45dbx.h" +#include "at45dbx.h" +#include "printf-stdarg.h" + +#if AT45DBX_MEM_CNT > 4 + #error AT45DBX_MEM_CNT must not exceed 4 +#endif + + +//_____ D E F I N I T I O N S ______________________________________________ + +/*! \name AT45DBX Group A Commands + */ +//! @{ +#define AT45DBX_CMDA_RD_PAGE 0xD2 //!< Main Memory Page Read (Serial/8-bit Mode). +#define AT45DBX_CMDA_RD_ARRAY_LEG 0xE8 //!< Continuous Array Read, Legacy Command (Serial/8-bit Mode). +#define AT45DBX_CMDA_RD_ARRAY_LF_SM 0x03 //!< Continuous Array Read, Low-Frequency Mode (Serial Mode). +#define AT45DBX_CMDA_RD_ARRAY_AF_SM 0x0B //!< Continuous Array Read, Any-Frequency Mode (Serial Mode). +#define AT45DBX_CMDA_RD_SECTOR_PROT_REG 0x32 //!< Read Sector Protection Register (Serial/8-bit Mode). +#define AT45DBX_CMDA_RD_SECTOR_LKDN_REG 0x35 //!< Read Sector Lockdown Register (Serial/8-bit Mode). +#define AT45DBX_CMDA_RD_SECURITY_REG 0x77 //!< Read Security Register (Serial/8-bit Mode). +//! @} + +/*! \name AT45DBX Group B Commands + */ +//! @{ +#define AT45DBX_CMDB_ER_PAGE 0x81 //!< Page Erase (Serial/8-bit Mode). +#define AT45DBX_CMDB_ER_BLOCK 0x50 //!< Block Erase (Serial/8-bit Mode). +#define AT45DBX_CMDB_ER_SECTOR 0x7C //!< Sector Erase (Serial/8-bit Mode). +#define AT45DBX_CMDB_ER_CHIP 0xC794809A //!< Chip Erase (Serial/8-bit Mode). +#define AT45DBX_CMDB_XFR_PAGE_TO_BUF1 0x53 //!< Main Memory Page to Buffer 1 Transfer (Serial/8-bit Mode). +#define AT45DBX_CMDB_XFR_PAGE_TO_BUF2 0x55 //!< Main Memory Page to Buffer 2 Transfer (Serial/8-bit Mode). +#define AT45DBX_CMDB_CMP_PAGE_TO_BUF1 0x60 //!< Main Memory Page to Buffer 1 Compare (Serial/8-bit Mode). +#define AT45DBX_CMDB_CMP_PAGE_TO_BUF2 0x61 //!< Main Memory Page to Buffer 2 Compare (Serial/8-bit Mode). +#define AT45DBX_CMDB_PR_BUF1_TO_PAGE_ER 0x83 //!< Buffer 1 to Main Memory Page Program with Built-in Erase (Serial/8-bit Mode). +#define AT45DBX_CMDB_PR_BUF2_TO_PAGE_ER 0x86 //!< Buffer 2 to Main Memory Page Program with Built-in Erase (Serial/8-bit Mode). +#define AT45DBX_CMDB_PR_BUF1_TO_PAGE 0x88 //!< Buffer 1 to Main Memory Page Program without Built-in Erase (Serial/8-bit Mode). +#define AT45DBX_CMDB_PR_BUF2_TO_PAGE 0x89 //!< Buffer 2 to Main Memory Page Program without Built-in Erase (Serial/8-bit Mode). +#define AT45DBX_CMDB_PR_PAGE_TH_BUF1 0x82 //!< Main Memory Page Program through Buffer 1 (Serial/8-bit Mode). +#define AT45DBX_CMDB_PR_PAGE_TH_BUF2 0x85 //!< Main Memory Page Program through Buffer 2 (Serial/8-bit Mode). +#define AT45DBX_CMDB_RWR_PAGE_TH_BUF1 0x58 //!< Auto Page Rewrite through Buffer 1 (Serial/8-bit Mode). +#define AT45DBX_CMDB_RWR_PAGE_TH_BUF2 0x59 //!< Auto Page Rewrite through Buffer 2 (Serial/8-bit Mode). +//! @} + +/*! \name AT45DBX Group C Commands + */ +//! @{ +#define AT45DBX_CMDC_RD_BUF1_LF_SM 0xD1 //!< Buffer 1 Read, Low-Frequency Mode (Serial Mode). +#define AT45DBX_CMDC_RD_BUF2_LF_SM 0xD3 //!< Buffer 2 Read, Low-Frequency Mode (Serial Mode). +#define AT45DBX_CMDC_RD_BUF1_AF_SM 0xD4 //!< Buffer 1 Read, Any-Frequency Mode (Serial Mode). +#define AT45DBX_CMDC_RD_BUF2_AF_SM 0xD6 //!< Buffer 2 Read, Any-Frequency Mode (Serial Mode). +#define AT45DBX_CMDC_RD_BUF1_AF_8M 0x54 //!< Buffer 1 Read, Any-Frequency Mode (8-bit Mode). +#define AT45DBX_CMDC_RD_BUF2_AF_8M 0x56 //!< Buffer 2 Read, Any-Frequency Mode (8-bit Mode). +#define AT45DBX_CMDC_WR_BUF1 0x84 //!< Buffer 1 Write (Serial/8-bit Mode). +#define AT45DBX_CMDC_WR_BUF2 0x87 //!< Buffer 2 Write (Serial/8-bit Mode). +#define AT45DBX_CMDC_RD_STATUS_REG 0xD7 //!< Status Register Read (Serial/8-bit Mode). +#define AT45DBX_CMDC_RD_MNFCT_DEV_ID_SM 0x9F //!< Manufacturer and Device ID Read (Serial Mode). +//! @} + +/*! \name AT45DBX Group D Commands + */ +//! @{ +#define AT45DBX_CMDD_EN_SECTOR_PROT 0x3D2A7FA9 //!< Enable Sector Protection (Serial/8-bit Mode). +#define AT45DBX_CMDD_DIS_SECTOR_PROT 0x3D2A7F9A //!< Disable Sector Protection (Serial/8-bit Mode). +#define AT45DBX_CMDD_ER_SECTOR_PROT_REG 0x3D2A7FCF //!< Erase Sector Protection Register (Serial/8-bit Mode). +#define AT45DBX_CMDD_PR_SECTOR_PROT_REG 0x3D2A7FFC //!< Program Sector Protection Register (Serial/8-bit Mode). +#define AT45DBX_CMDD_LKDN_SECTOR 0x3D2A7F30 //!< Sector Lockdown (Serial/8-bit Mode). +#define AT45DBX_CMDD_PR_SECURITY_REG 0x9B000000 //!< Program Security Register (Serial/8-bit Mode). +#define AT45DBX_CMDD_PR_CONF_REG 0x3D2A80A6 //!< Program Configuration Register (Serial/8-bit Mode). +#define AT45DBX_CMDD_DEEP_PWR_DN 0xB9 //!< Deep Power-down (Serial/8-bit Mode). +#define AT45DBX_CMDD_RSM_DEEP_PWR_DN 0xAB //!< Resume from Deep Power-down (Serial/8-bit Mode). +//! @} + + +/*! \name Bit-Masks and Values for the Status Register + */ +//! @{ +#define AT45DBX_MSK_BUSY 0x80 //!< Busy status bit-mask. +#define AT45DBX_BUSY 0x00 //!< Busy status value (0x00 when busy, 0x80 when ready). +#define AT45DBX_MSK_DENSITY 0x3C //!< Device density bit-mask. +//! @} +#if AT45DBX_MEM_SIZE == AT45DBX_1MB + +/*! \name AT45DB081 Memories + */ +//! @{ +#define AT45DB021D_DENSITY 0x14 //!< Device density value. +#define AT45DBX_DENSITY 0x24 //!< Device density value. +#define AT45DBX_BYTE_ADDR_BITS 9 //!< Address bits for byte position within buffer. + +//! @} +#elif AT45DBX_MEM_SIZE == AT45DBX_2MB +/*! \name AT45DB021D Memories + */ +//! @{ +#define AT45DBX_DENSITY 0x21 //!< Device density value. +#define AT45DBX_BYTE_ADDR_BITS 10 //!< Address bits for byte position within buffer. + +//! @} +#if 0 +/*! \name AT45DB161 Memories + */ +//! @{ +#define AT45DBX_DENSITY 0x2C //!< Device density value. +#define AT45DBX_BYTE_ADDR_BITS 10 //!< Address bits for byte position within buffer. + +//! @} +#endif + +#elif AT45DBX_MEM_SIZE == AT45DBX_4MB + +/*! \name AT45DB321 Memories + */ +//! @{ +#define AT45DBX_DENSITY 0x34 //!< Device density value. +#define AT45DBX_BYTE_ADDR_BITS 10 //!< Address bits for byte position within buffer. + +//! @} + +#elif AT45DBX_MEM_SIZE == AT45DBX_8MB + +/*! \name AT45DB642 Memories + */ +//! @{ +#define AT45DBX_DENSITY 0x3C //!< Device density value. +#define AT45DBX_BYTE_ADDR_BITS 11 //!< Address bits for byte position within buffer. + + +//! @} + +#else + #error AT45DBX_MEM_SIZE is not defined to a supported value +#endif + + + +//! Address bits for page selection. +#define AT45DBX_PAGE_ADDR_BITS (AT45DBX_MEM_SIZE - AT45DBX_PAGE_BITS) + +//! Number of bits for addresses within pages. +#define AT45DBX_PAGE_BITS (AT45DBX_BYTE_ADDR_BITS - 1) + +//! Page size in bytes. +#define AT45DBX_PAGE_SIZE (1 << AT45DBX_PAGE_BITS) + +//! Bit-mask for byte position within buffer in \ref gl_ptr_mem. +#define AT45DBX_MSK_PTR_BYTE ((1 << AT45DBX_PAGE_BITS) - 1) + +//! Bit-mask for page selection in \ref gl_ptr_mem. +#define AT45DBX_MSK_PTR_PAGE (((1 << AT45DBX_PAGE_ADDR_BITS) - 1) << AT45DBX_PAGE_BITS) + +//! Bit-mask for byte position within sector in \ref gl_ptr_mem. +#define AT45DBX_MSK_PTR_SECTOR ((1 << AT45DBX_SECTOR_BITS) - 1) + + +/*! \brief Sends a dummy byte through SPI. + */ +#define spi_write_dummy() spi_write(AT45DBX_SPI, 0xFF) + + +//! Boolean indicating whether memory is in busy state. +static Bool at45dbx_busy; + +//! Memory data pointer. +static U32 gl_ptr_mem; + +//! Sector buffer. +static U8 sector_buf[AT45DBX_SECTOR_SIZE]; + + +/*! \name Control Functions + */ +//! @{ + + +Bool at45dbx_init(spi_options_t spiOptions, unsigned int pba_hz) +{ + // Setup SPI registers according to spiOptions. + for (spiOptions.reg = AT45DBX_SPI_FIRST_NPCS; + spiOptions.reg < AT45DBX_SPI_FIRST_NPCS + AT45DBX_MEM_CNT; + spiOptions.reg++) + { + if (spi_setupChipReg(AT45DBX_SPI, &spiOptions, pba_hz) != SPI_OK) return KO; + } + + // Memory ready. + at45dbx_busy = FALSE; + + return OK; +} + + +/*! \brief Selects or unselects a DF memory. + * + * \param memidx Memory ID of DF to select or unselect. + * \param bSelect Boolean indicating whether the DF memory has to be selected. + */ +static void at45dbx_chipselect_df(U8 memidx, Bool bSelect) +{ + if (bSelect) + { + // Select SPI chip. + spi_selectChip(AT45DBX_SPI, AT45DBX_SPI_FIRST_NPCS + memidx); + } + else + { + // Unselect SPI chip. + spi_unselectChip(AT45DBX_SPI, AT45DBX_SPI_FIRST_NPCS + memidx); + } +} + + +Bool at45dbx_mem_check(void) +{ + U8 df; + U16 status = 0; + + // DF memory check. + for (df = 0; df < AT45DBX_MEM_CNT; df++) + { + // Select the DF memory to check. + at45dbx_chipselect_df(df, TRUE); + + // Send the Status Register Read command. + spi_write(AT45DBX_SPI, AT45DBX_CMDC_RD_STATUS_REG); + + // Send a dummy byte to read the status register. + spi_write_dummy(); + spi_read(AT45DBX_SPI, &status); + + // Unselect the checked DF memory. + at45dbx_chipselect_df(df, FALSE); + + // Unexpected device density value. + if ((status & AT45DBX_MSK_DENSITY) < AT45DB021D_DENSITY) + { + printk("Unexpected device density value: %d (0x%x)\n", (status & AT45DBX_MSK_DENSITY), status); + return KO; + } + } + + return OK; +} + + +/*! \brief Waits until the DF is ready. + */ +static void at45dbx_wait_ready(void) +{ + U16 status; + + // Select the DF memory gl_ptr_mem points to. + at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, TRUE); + + // Send the Status Register Read command. + spi_write(AT45DBX_SPI, AT45DBX_CMDC_RD_STATUS_REG); + + // Read the status register until the DF is ready. + do + { + // Send a dummy byte to read the status register. + spi_write_dummy(); + spi_read(AT45DBX_SPI, &status); + } while ((status & AT45DBX_MSK_BUSY) == AT45DBX_BUSY); + + // Unselect the DF memory gl_ptr_mem points to. + at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE); +} + + +Bool at45dbx_read_open(U32 sector) +{ + U32 addr; + + // Set the global memory pointer to a byte address. + gl_ptr_mem = sector << AT45DBX_SECTOR_BITS; // gl_ptr_mem = sector * AT45DBX_SECTOR_SIZE. + + // If the DF memory is busy, wait until it's ready. + if (at45dbx_busy) at45dbx_wait_ready(); + at45dbx_busy = FALSE; + + // Select the DF memory gl_ptr_mem points to. + at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, TRUE); + + // Initiate a page read at a given sector. + + // Send the Main Memory Page Read command. + spi_write(AT45DBX_SPI, AT45DBX_CMDA_RD_PAGE); + + // Send the three address bytes, which comprise: + // - (24 - (AT45DBX_PAGE_ADDR_BITS + AT45DBX_BYTE_ADDR_BITS)) reserved bits; + // - then AT45DBX_PAGE_ADDR_BITS bits specifying the page in main memory to be read; + // - then AT45DBX_BYTE_ADDR_BITS bits specifying the starting byte address within that page. + // NOTE: The bits of gl_ptr_mem above the AT45DBX_MEM_SIZE bits are useless for the local + // DF addressing. They are used for DF discrimination when there are several DFs. + addr = (Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_PAGE) << AT45DBX_BYTE_ADDR_BITS) | + Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_BYTE); + spi_write(AT45DBX_SPI, LSB2W(addr)); + spi_write(AT45DBX_SPI, LSB1W(addr)); + spi_write(AT45DBX_SPI, LSB0W(addr)); + + // Send 32 don't care clock cycles to initialize the read operation. + spi_write_dummy(); + spi_write_dummy(); + spi_write_dummy(); + spi_write_dummy(); + + return OK; +} + + +void at45dbx_read_close(void) +{ + // Unselect the DF memory gl_ptr_mem points to. + at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE); + + // Memory ready. + at45dbx_busy = FALSE; +} + + +Bool at45dbx_write_open(U32 sector) +{ + U32 addr; + + // Set the global memory pointer to a byte address. + gl_ptr_mem = sector << AT45DBX_SECTOR_BITS; // gl_ptr_mem = sector * AT45DBX_SECTOR_SIZE. + + // If the DF memory is busy, wait until it's ready. + if (at45dbx_busy) at45dbx_wait_ready(); + at45dbx_busy = FALSE; + +#if AT45DBX_PAGE_SIZE > AT45DBX_SECTOR_SIZE + // Select the DF memory gl_ptr_mem points to. + at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, TRUE); + + // Transfer the content of the current page to buffer 1. + + // Send the Main Memory Page to Buffer 1 Transfer command. + spi_write(AT45DBX_SPI, AT45DBX_CMDB_XFR_PAGE_TO_BUF1); + + // Send the three address bytes, which comprise: + // - (24 - (AT45DBX_PAGE_ADDR_BITS + AT45DBX_BYTE_ADDR_BITS)) reserved bits; + // - then AT45DBX_PAGE_ADDR_BITS bits specifying the page in main memory to be read; + // - then AT45DBX_BYTE_ADDR_BITS don't care bits. + // NOTE: The bits of gl_ptr_mem above the AT45DBX_MEM_SIZE bits are useless for the local + // DF addressing. They are used for DF discrimination when there are several DFs. + addr = Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_PAGE) << AT45DBX_BYTE_ADDR_BITS; + spi_write(AT45DBX_SPI, LSB2W(addr)); + spi_write(AT45DBX_SPI, LSB1W(addr)); + spi_write(AT45DBX_SPI, LSB0W(addr)); + + // Unselect the DF memory gl_ptr_mem points to. + at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE); + + // Wait for end of page transfer. + at45dbx_wait_ready(); +#endif + + // Select the DF memory gl_ptr_mem points to. + at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, TRUE); + + // Initiate a page write at a given sector. + + // Send the Main Memory Page Program through Buffer 1 command. + spi_write(AT45DBX_SPI, AT45DBX_CMDB_PR_PAGE_TH_BUF1); + + // Send the three address bytes, which comprise: + // - (24 - (AT45DBX_PAGE_ADDR_BITS + AT45DBX_BYTE_ADDR_BITS)) reserved bits; + // - then AT45DBX_PAGE_ADDR_BITS bits specifying the page in main memory to be written; + // - then AT45DBX_BYTE_ADDR_BITS bits specifying the starting byte address within that page. + // NOTE: The bits of gl_ptr_mem above the AT45DBX_MEM_SIZE bits are useless for the local + // DF addressing. They are used for DF discrimination when there are several DFs. + addr = (Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_PAGE) << AT45DBX_BYTE_ADDR_BITS) | + Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_BYTE); + spi_write(AT45DBX_SPI, LSB2W(addr)); + spi_write(AT45DBX_SPI, LSB1W(addr)); + spi_write(AT45DBX_SPI, LSB0W(addr)); + + return OK; +} + + +void at45dbx_write_close(void) +{ + // While end of logical sector not reached, zero-fill remaining memory bytes. + while (Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_SECTOR)) + { + spi_write(AT45DBX_SPI, 0x00); + gl_ptr_mem++; + } + + // Unselect the DF memory gl_ptr_mem points to. + at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE); + + // Memory busy. + at45dbx_busy = TRUE; +} + + +//! @} + + +/*! \name Single-Byte Access Functions + */ +//! @{ + + +U8 at45dbx_read_byte(void) +{ + U16 data; + + // Memory busy. + if (at45dbx_busy) + { + // Being here, we know that we previously finished a page read. + // => We have to access the next page. + + // Memory ready. + at45dbx_busy = FALSE; + + // Eventually select the next DF and open the next page. + // NOTE: at45dbx_read_open input parameter is a sector. + at45dbx_read_open(gl_ptr_mem >> AT45DBX_SECTOR_BITS); // gl_ptr_mem / AT45DBX_SECTOR_SIZE. + } + + // Send a dummy byte to read the next data byte. + spi_write_dummy(); + spi_read(AT45DBX_SPI, &data); + gl_ptr_mem++; + + // If end of page reached, + if (!Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_BYTE)) + { + // unselect the DF memory gl_ptr_mem points to. + at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE); + + // Memory busy. + at45dbx_busy = TRUE; + } + + return data; +} + + +Bool at45dbx_write_byte(U8 b) +{ + // Memory busy. + if (at45dbx_busy) + { + // Being here, we know that we previously launched a page programming. + // => We have to access the next page. + + // Eventually select the next DF and open the next page. + // NOTE: at45dbx_write_open input parameter is a sector. + at45dbx_write_open(gl_ptr_mem >> AT45DBX_SECTOR_BITS); // gl_ptr_mem / AT45DBX_SECTOR_SIZE. + } + + // Write the next data byte. + spi_write(AT45DBX_SPI, b); + gl_ptr_mem++; + + // If end of page reached, + if (!Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_BYTE)) + { + // unselect the DF memory gl_ptr_mem points to in order to program the page. + at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE); + + // Memory busy. + at45dbx_busy = TRUE; + } + + return OK; +} + + +//! @} + + +/*! \name Multiple-Sector Access Functions + */ +//! @{ + + +Bool at45dbx_read_multiple_sector(U16 nb_sector) +{ + while (nb_sector--) + { + // Read the next sector. + at45dbx_read_sector_2_ram(sector_buf); + at45dbx_read_multiple_sector_callback(sector_buf); + } + + return OK; +} + + +Bool at45dbx_write_multiple_sector(U16 nb_sector) +{ + while (nb_sector--) + { + // Write the next sector. + at45dbx_write_multiple_sector_callback(sector_buf); + at45dbx_write_sector_from_ram(sector_buf); + } + + return OK; +} + + +//! @} + + +/*! \name Single-Sector Access Functions + */ +//! @{ + + +Bool at45dbx_read_sector_2_ram(void *ram) +{ + U8 *_ram = ram; + U16 i; + U16 data; + + // Memory busy. + if (at45dbx_busy) + { + // Being here, we know that we previously finished a page read. + // => We have to access the next page. + + // Memory ready. + at45dbx_busy = FALSE; + + // Eventually select the next DF and open the next page. + // NOTE: at45dbx_read_open input parameter is a sector. + at45dbx_read_open(gl_ptr_mem >> AT45DBX_SECTOR_BITS); // gl_ptr_mem / AT45DBX_SECTOR_SIZE. + } + + // Read the next sector. + for (i = AT45DBX_SECTOR_SIZE; i; i--) + { + // Send a dummy byte to read the next data byte. + spi_write_dummy(); + spi_read(AT45DBX_SPI, &data); + *_ram++ = data; + } + + // Update the memory pointer. + gl_ptr_mem += AT45DBX_SECTOR_SIZE; + +#if AT45DBX_PAGE_SIZE > AT45DBX_SECTOR_SIZE + // If end of page reached, + if (!Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_BYTE)) +#endif + { + // unselect the DF memory gl_ptr_mem points to. + at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE); + + // Memory busy. + at45dbx_busy = TRUE; + } + + return OK; +} + + +Bool at45dbx_write_sector_from_ram(const void *ram) +{ + const U8 *_ram = ram; + U16 i; + + // Memory busy. + if (at45dbx_busy) + { + // Being here, we know that we previously launched a page programming. + // => We have to access the next page. + + // Eventually select the next DF and open the next page. + // NOTE: at45dbx_write_open input parameter is a sector. + at45dbx_write_open(gl_ptr_mem >> AT45DBX_SECTOR_BITS); // gl_ptr_mem / AT45DBX_SECTOR_SIZE. + } + + // Write the next sector. + for (i = AT45DBX_SECTOR_SIZE; i; i--) + { + // Write the next data byte. + spi_write(AT45DBX_SPI, *_ram++); + } + + // Update the memory pointer. + gl_ptr_mem += AT45DBX_SECTOR_SIZE; + +#if AT45DBX_PAGE_SIZE > AT45DBX_SECTOR_SIZE + // If end of page reached, + if (!Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_BYTE)) +#endif + { + // unselect the DF memory gl_ptr_mem points to in order to program the page. + at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE); + + // Memory busy. + at45dbx_busy = TRUE; + } + + return OK; +} + + +//! @} + + +#endif // AT45DBX_MEM == ENABLE diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx.h new file mode 100644 index 0000000..5816b61 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx.h @@ -0,0 +1,269 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Management of the AT45DBX data flash controller through SPI. + * + * This file manages the accesses to the AT45DBX data flash components. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an SPI module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _AT45DBX_H_ +#define _AT45DBX_H_ + + +#include "conf_access.h" + +#if AT45DBX_MEM == DISABLE + #error at45dbx.h is #included although AT45DBX_MEM is disabled +#endif + + +#include "spi.h" + + +//_____ D E F I N I T I O N S ______________________________________________ + +/*! \name Available AT45DBX Sizes + * + * Number of address bits of available AT45DBX data flash memories. + * + * \note Only memories with page sizes of at least 512 bytes (sector size) are + * supported. + */ +//! @{ +#define AT45DBX_1MB 20 +#define AT45DBX_2MB 21 +#define AT45DBX_4MB 22 +#define AT45DBX_8MB 23 +//! @} + +// AT45DBX_1MB +#define AT45DBX_SECTOR_BITS 8 //! Number of bits for addresses within sectors. +// AT45DBX_2MB AT45DBX_4MB AT45DBX_8MB +//#define AT45DBX_SECTOR_BITS 9 //! Number of bits for addresses within sectors. + +//! Sector size in bytes. +#define AT45DBX_SECTOR_SIZE (1 << AT45DBX_SECTOR_BITS) + +//_____ D E C L A R A T I O N S ____________________________________________ + +/*! \name Control Functions + */ +//! @{ + +/*! \brief Initializes the data flash controller and the SPI channel by which + * the DF is controlled. + * + * \param spiOptions Initialization options of the DF SPI channel. + * \param pba_hz SPI module input clock frequency (PBA clock, Hz). + * + * \retval OK Success. + * \retval KO Failure. + */ +extern Bool at45dbx_init(spi_options_t spiOptions, unsigned int pba_hz); + +/*! \brief Performs a memory check on all DFs. + * + * \retval OK Success. + * \retval KO Failure. + */ +extern Bool at45dbx_mem_check(void); + +/*! \brief Opens a DF memory in read mode at a given sector. + * + * \param sector Start sector. + * + * \retval OK Success. + * \retval KO Failure. + * + * \note Sector may be page-unaligned (depending on the DF page size). + */ +extern Bool at45dbx_read_open(U32 sector); + +/*! \brief Unselects the current DF memory. + */ +extern void at45dbx_read_close(void); + +/*! \brief This function opens a DF memory in write mode at a given sector. + * + * \param sector Start sector. + * + * \retval OK Success. + * \retval KO Failure. + * + * \note Sector may be page-unaligned (depending on the DF page size). + * + * \note If \ref AT45DBX_PAGE_SIZE > \ref AT45DBX_SECTOR_SIZE, page content is + * first loaded in buffer to then be partially updated by write byte or + * write sector functions. + */ +extern Bool at45dbx_write_open(U32 sector); + +/*! \brief Fills the end of the current logical sector and launches page programming. + */ +extern void at45dbx_write_close(void); + +//! @} + + +/*! \name Single-Byte Access Functions + */ +//! @{ + +/*! \brief Performs a single byte read from DF memory. + * + * \return The read byte. + * + * \note First call must be preceded by a call to the \ref at45dbx_read_open + * function. + */ +extern U8 at45dbx_read_byte(void); + +/*! \brief Performs a single byte write to DF memory. + * + * \param b The byte to write. + * + * \retval OK Success. + * \retval KO Failure. + * + * \note First call must be preceded by a call to the \ref at45dbx_write_open + * function. + */ +extern Bool at45dbx_write_byte(U8 b); + +//! @} + + +/*! \name Multiple-Sector Access Functions + */ +//! @{ + +/*! \brief Reads \a nb_sector sectors from DF memory. + * + * Data flow is: DF -> callback. + * + * \param nb_sector Number of contiguous sectors to read. + * + * \retval OK Success. + * \retval KO Failure. + * + * \note First call must be preceded by a call to the \ref at45dbx_read_open + * function. + * + * \note As \ref AT45DBX_PAGE_SIZE is always a multiple of + * \ref AT45DBX_SECTOR_SIZE, there is no need to check page end for each + * byte. + */ +extern Bool at45dbx_read_multiple_sector(U16 nb_sector); + +/*! \brief Callback function invoked after each sector read during + * \ref at45dbx_read_multiple_sector. + * + * \param psector Pointer to read sector. + */ +extern void at45dbx_read_multiple_sector_callback(const void *psector); + +/*! \brief Writes \a nb_sector sectors to DF memory. + * + * Data flow is: callback -> DF. + * + * \param nb_sector Number of contiguous sectors to write. + * + * \retval OK Success. + * \retval KO Failure. + * + * \note First call must be preceded by a call to the \ref at45dbx_write_open + * function. + * + * \note As \ref AT45DBX_PAGE_SIZE is always a multiple of + * \ref AT45DBX_SECTOR_SIZE, there is no need to check page end for each + * byte. + */ +extern Bool at45dbx_write_multiple_sector(U16 nb_sector); + +/*! \brief Callback function invoked before each sector write during + * \ref at45dbx_write_multiple_sector. + * + * \param psector Pointer to sector to write. + */ +extern void at45dbx_write_multiple_sector_callback(void *psector); + +//! @} + + +/*! \name Single-Sector Access Functions + */ +//! @{ + +/*! \brief Reads 1 DF sector to a RAM buffer. + * + * Data flow is: DF -> RAM. + * + * \param ram Pointer to RAM buffer. + * + * \retval OK Success. + * \retval KO Failure. + * + * \note First call must be preceded by a call to the \ref at45dbx_read_open + * function. + */ +extern Bool at45dbx_read_sector_2_ram(void *ram); + +/*! \brief Writes 1 DF sector from a RAM buffer. + * + * Data flow is: RAM -> DF. + * + * \param ram Pointer to RAM buffer. + * + * \retval OK Success. + * \retval KO Failure. + * + * \note First call must be preceded by a call to the \ref at45dbx_write_open + * function. + */ +extern Bool at45dbx_write_sector_from_ram(const void *ram); + +//! @} + + +#endif // _AT45DBX_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx_mem.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx_mem.c new file mode 100644 index 0000000..4c0ace2 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx_mem.c @@ -0,0 +1,234 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief CTRL_ACCESS interface for the AT45DBX data flash controller. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an SPI module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +//_____ I N C L U D E S ___________________________________________________ + +#include "conf_access.h" + + +#if AT45DBX_MEM == ENABLE + +#include "conf_at45dbx.h" +#include "at45dbx.h" +#include "at45dbx_mem.h" + + +//_____ D E F I N I T I O N S ______________________________________________ + +//! Whether to detect write accesses to the memory. +#define AT45DBX_MEM_TEST_CHANGE_STATE ENABLED + + +#if (ACCESS_USB == ENABLED || ACCESS_MEM_TO_RAM == ENABLED) && AT45DBX_MEM_TEST_CHANGE_STATE == ENABLED + +//! Memory data modified flag. +static volatile Bool s_b_data_modify = FALSE; + +#endif + + +/*! \name Control Interface + */ +//! @{ + + +Ctrl_status at45dbx_test_unit_ready(void) +{ + return (at45dbx_mem_check() == OK) ? CTRL_GOOD : CTRL_NO_PRESENT; +} + + +Ctrl_status at45dbx_read_capacity(U32 *u32_nb_sector) +{ + *u32_nb_sector = (AT45DBX_MEM_CNT << (AT45DBX_MEM_SIZE - AT45DBX_SECTOR_BITS)) - 1; + + return CTRL_GOOD; +} + + +Bool at45dbx_wr_protect(void) +{ + return FALSE; +} + + +Bool at45dbx_removal(void) +{ + return FALSE; +} + + +//! @} + + +#if ACCESS_USB == ENABLED + +#include "usb_drv.h" +#include "scsi_decoder.h" + + +/*! \name MEM <-> USB Interface + */ +//! @{ + + +Ctrl_status at45dbx_usb_read_10(U32 addr, U16 nb_sector) +{ + if (addr + nb_sector > AT45DBX_MEM_CNT << (AT45DBX_MEM_SIZE - AT45DBX_SECTOR_BITS)) return CTRL_FAIL; + + at45dbx_read_open(addr); + at45dbx_read_multiple_sector(nb_sector); + at45dbx_read_close(); + + return CTRL_GOOD; +} + + +void at45dbx_read_multiple_sector_callback(const void *psector) +{ + U16 data_to_transfer = AT45DBX_SECTOR_SIZE; + + // Transfer read sector to the USB interface. + while (data_to_transfer) + { + while (!Is_usb_in_ready(g_scsi_ep_ms_in)) + { + if(!Is_usb_endpoint_enabled(g_scsi_ep_ms_in)) + return; // USB Reset + } + + Usb_reset_endpoint_fifo_access(g_scsi_ep_ms_in); + data_to_transfer = usb_write_ep_txpacket(g_scsi_ep_ms_in, psector, + data_to_transfer, &psector); + Usb_ack_in_ready_send(g_scsi_ep_ms_in); + } +} + + +Ctrl_status at45dbx_usb_write_10(U32 addr, U16 nb_sector) +{ + if (addr + nb_sector > AT45DBX_MEM_CNT << (AT45DBX_MEM_SIZE - AT45DBX_SECTOR_BITS)) return CTRL_FAIL; + +#if AT45DBX_MEM_TEST_CHANGE_STATE == ENABLED + if (nb_sector) s_b_data_modify = TRUE; +#endif + + at45dbx_write_open(addr); + at45dbx_write_multiple_sector(nb_sector); + at45dbx_write_close(); + + return CTRL_GOOD; +} + + +void at45dbx_write_multiple_sector_callback(void *psector) +{ + U16 data_to_transfer = AT45DBX_SECTOR_SIZE; + + // Transfer sector to write from the USB interface. + while (data_to_transfer) + { + while (!Is_usb_out_received(g_scsi_ep_ms_out)) + { + if(!Is_usb_endpoint_enabled(g_scsi_ep_ms_out)) + return; // USB Reset + } + + Usb_reset_endpoint_fifo_access(g_scsi_ep_ms_out); + data_to_transfer = usb_read_ep_rxpacket(g_scsi_ep_ms_out, psector, + data_to_transfer, &psector); + Usb_ack_out_received_free(g_scsi_ep_ms_out); + } +} + + +//! @} + +#endif // ACCESS_USB == ENABLED + + +#if ACCESS_MEM_TO_RAM == ENABLED + +/*! \name MEM <-> RAM Interface + */ +//! @{ + + +Ctrl_status at45dbx_df_2_ram(U32 addr, void *ram) +{ + if (addr + 1 > AT45DBX_MEM_CNT << (AT45DBX_MEM_SIZE - AT45DBX_SECTOR_BITS)) return CTRL_FAIL; + + at45dbx_read_open(addr); + at45dbx_read_sector_2_ram(ram); + at45dbx_read_close(); + + return CTRL_GOOD; +} + + +Ctrl_status at45dbx_ram_2_df(U32 addr, const void *ram) +{ + if (addr + 1 > AT45DBX_MEM_CNT << (AT45DBX_MEM_SIZE - AT45DBX_SECTOR_BITS)) return CTRL_FAIL; + +#if AT45DBX_MEM_TEST_CHANGE_STATE == ENABLED + s_b_data_modify = TRUE; +#endif + + at45dbx_write_open(addr); + at45dbx_write_sector_from_ram(ram); + at45dbx_write_close(); + + return CTRL_GOOD; +} + + +//! @} + +#endif // ACCESS_MEM_TO_RAM == ENABLED + + +#endif // AT45DBX_MEM == ENABLE diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx_mem.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx_mem.h new file mode 100644 index 0000000..de24fa3 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx_mem.h @@ -0,0 +1,164 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief CTRL_ACCESS interface for the AT45DBX data flash controller. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an SPI module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _AT45DBX_MEM_H_ +#define _AT45DBX_MEM_H_ + + +#include "conf_access.h" + +#if AT45DBX_MEM == DISABLE + #error at45dbx_mem.h is #included although AT45DBX_MEM is disabled +#endif + + +#include "ctrl_access.h" + + +//_____ D E C L A R A T I O N S ____________________________________________ + +/*! \name Control Interface + */ +//! @{ + +/*! \brief Tests the memory state and initializes the memory if required. + * + * The TEST UNIT READY SCSI primary command allows an application client to poll + * a LUN until it is ready without having to allocate memory for returned data. + * + * This command may be used to check the media status of LUNs with removable + * media. + * + * \return Status. + */ +extern Ctrl_status at45dbx_test_unit_ready(void); + +/*! \brief Returns the address of the last valid sector in the memory. + * + * \param u32_nb_sector Pointer to the address of the last valid sector. + * + * \return Status. + */ +extern Ctrl_status at45dbx_read_capacity(U32 *u32_nb_sector); + +/*! \brief Returns the write-protection state of the memory. + * + * \return \c TRUE if the memory is write-protected, else \c FALSE. + * + * \note Only used by removable memories with hardware-specific write + * protection. + */ +extern Bool at45dbx_wr_protect(void); + +/*! \brief Tells whether the memory is removable. + * + * \return \c TRUE if the memory is removable, else \c FALSE. + */ +extern Bool at45dbx_removal(void); + +//! @} + + +#if ACCESS_USB == ENABLED + +/*! \name MEM <-> USB Interface + */ +//! @{ + +/*! \brief Tranfers data from the memory to USB. + * + * \param addr Address of first memory sector to read. + * \param nb_sector Number of sectors to transfer. + * + * \return Status. + */ +extern Ctrl_status at45dbx_usb_read_10(U32 addr, U16 nb_sector); + +/*! \brief Tranfers data from USB to the memory. + * + * \param addr Address of first memory sector to write. + * \param nb_sector Number of sectors to transfer. + * + * \return Status. + */ +extern Ctrl_status at45dbx_usb_write_10(U32 addr, U16 nb_sector); + +//! @} + +#endif + + +#if ACCESS_MEM_TO_RAM == ENABLED + +/*! \name MEM <-> RAM Interface + */ +//! @{ + +/*! \brief Copies 1 data sector from the memory to RAM. + * + * \param addr Address of first memory sector to read. + * \param ram Pointer to RAM buffer to write. + * + * \return Status. + */ +extern Ctrl_status at45dbx_df_2_ram(U32 addr, void *ram); + +/*! \brief Copies 1 data sector from RAM to the memory. + * + * \param addr Address of first memory sector to write. + * \param ram Pointer to RAM buffer to read. + * + * \return Status. + */ +extern Ctrl_status at45dbx_ram_2_df(U32 addr, const void *ram); + +//! @} + +#endif + + +#endif // _AT45DBX_MEM_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC/flashc.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC/flashc.c new file mode 100644 index 0000000..2eee15c --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC/flashc.c @@ -0,0 +1,1117 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FLASHC driver for AVR32 UC3. + * + * AVR32 Flash Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a FLASHC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include <avr32/io.h> +#include <stddef.h> +#include "compiler.h" +#include "flashc.h" + + +/*! \name FLASHC Writable Bit-Field Registers + */ +//! @{ + +typedef union +{ + unsigned long fcr; + avr32_flashc_fcr_t FCR; +} u_avr32_flashc_fcr_t; + +typedef union +{ + unsigned long fcmd; + avr32_flashc_fcmd_t FCMD; +} u_avr32_flashc_fcmd_t; + +//! @} + + +/*! \name Flash Properties + */ +//! @{ + + +unsigned int flashc_get_flash_size(void) +{ +#if (defined AVR32_FLASHC_300_H_INCLUDED) + static const unsigned int FLASH_SIZE[1 << AVR32_FLASHC_PR_FSZ_SIZE] = + { + 32 << 10, + 64 << 10, + 128 << 10, + 256 << 10, + 384 << 10, + 512 << 10, + 768 << 10, + 1024 << 10 + }; + return FLASH_SIZE[(AVR32_FLASHC.pr & AVR32_FLASHC_PR_FSZ_MASK) >> AVR32_FLASHC_PR_FSZ_OFFSET]; +#else + static const unsigned int FLASH_SIZE[1 << AVR32_FLASHC_FSR_FSZ_SIZE] = + { + 32 << 10, + 64 << 10, + 128 << 10, + 256 << 10, + 384 << 10, + 512 << 10, + 768 << 10, + 1024 << 10 + }; + return FLASH_SIZE[(AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FSZ_MASK) >> AVR32_FLASHC_FSR_FSZ_OFFSET]; +#endif +} + + +unsigned int flashc_get_page_count(void) +{ + return flashc_get_flash_size() / AVR32_FLASHC_PAGE_SIZE; +} + + +unsigned int flashc_get_page_count_per_region(void) +{ + return flashc_get_page_count() / AVR32_FLASHC_REGIONS; +} + + +unsigned int flashc_get_page_region(int page_number) +{ + return ((page_number >= 0) ? page_number : flashc_get_page_number()) / flashc_get_page_count_per_region(); +} + + +unsigned int flashc_get_region_first_page_number(unsigned int region) +{ + return region * flashc_get_page_count_per_region(); +} + + +//! @} + + +/*! \name FLASHC Control + */ +//! @{ + + +unsigned int flashc_get_wait_state(void) +{ + return (AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_FWS_MASK) >> AVR32_FLASHC_FCR_FWS_OFFSET; +} + + +void flashc_set_wait_state(unsigned int wait_state) +{ + u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr}; + u_avr32_flashc_fcr.FCR.fws = wait_state; + AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr; +} + + +Bool flashc_is_ready_int_enabled(void) +{ + return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_FRDY_MASK) != 0); +} + + +void flashc_enable_ready_int(Bool enable) +{ + u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr}; + u_avr32_flashc_fcr.FCR.frdy = (enable != FALSE); + AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr; +} + + +Bool flashc_is_lock_error_int_enabled(void) +{ + return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_LOCKE_MASK) != 0); +} + + +void flashc_enable_lock_error_int(Bool enable) +{ + u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr}; + u_avr32_flashc_fcr.FCR.locke = (enable != FALSE); + AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr; +} + + +Bool flashc_is_prog_error_int_enabled(void) +{ + return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_PROGE_MASK) != 0); +} + + +void flashc_enable_prog_error_int(Bool enable) +{ + u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr}; + u_avr32_flashc_fcr.FCR.proge = (enable != FALSE); + AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr; +} + + +//! @} + + +/*! \name FLASHC Status + */ +//! @{ + + +Bool flashc_is_ready(void) +{ + return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FRDY_MASK) != 0); +} + + +void flashc_default_wait_until_ready(void) +{ + while (!flashc_is_ready()); +} + + +void (*volatile flashc_wait_until_ready)(void) = flashc_default_wait_until_ready; + + +/*! \brief Gets the error status of the FLASHC. + * + * \return The error status of the FLASHC built up from + * \c AVR32_FLASHC_FSR_LOCKE_MASK and \c AVR32_FLASHC_FSR_PROGE_MASK. + * + * \warning This hardware error status is cleared by all functions reading the + * Flash Status Register (FSR). This function is therefore not part of + * the driver's API which instead presents \ref flashc_is_lock_error + * and \ref flashc_is_programming_error. + */ +static unsigned int flashc_get_error_status(void) +{ + return AVR32_FLASHC.fsr & (AVR32_FLASHC_FSR_LOCKE_MASK | + AVR32_FLASHC_FSR_PROGE_MASK); +} + + +//! Sticky error status of the FLASHC. +//! This variable is updated by functions that issue FLASHC commands. It +//! contains the cumulated FLASHC error status of all the FLASHC commands issued +//! by a function. +static unsigned int flashc_error_status = 0; + + +Bool flashc_is_lock_error(void) +{ + return ((flashc_error_status & AVR32_FLASHC_FSR_LOCKE_MASK) != 0); +} + + +Bool flashc_is_programming_error(void) +{ + return ((flashc_error_status & AVR32_FLASHC_FSR_PROGE_MASK) != 0); +} + + +//! @} + + +/*! \name FLASHC Command Control + */ +//! @{ + + +unsigned int flashc_get_command(void) +{ + return (AVR32_FLASHC.fcmd & AVR32_FLASHC_FCMD_CMD_MASK) >> AVR32_FLASHC_FCMD_CMD_OFFSET; +} + + +unsigned int flashc_get_page_number(void) +{ + return (AVR32_FLASHC.fcmd & AVR32_FLASHC_FCMD_PAGEN_MASK) >> AVR32_FLASHC_FCMD_PAGEN_OFFSET; +} + + +void flashc_issue_command(unsigned int command, int page_number) +{ + u_avr32_flashc_fcmd_t u_avr32_flashc_fcmd; + flashc_wait_until_ready(); + u_avr32_flashc_fcmd.fcmd = AVR32_FLASHC.fcmd; + u_avr32_flashc_fcmd.FCMD.cmd = command; + if (page_number >= 0) u_avr32_flashc_fcmd.FCMD.pagen = page_number; + u_avr32_flashc_fcmd.FCMD.key = AVR32_FLASHC_FCMD_KEY_KEY; + AVR32_FLASHC.fcmd = u_avr32_flashc_fcmd.fcmd; + flashc_error_status = flashc_get_error_status(); + flashc_wait_until_ready(); +} + + +//! @} + + +/*! \name FLASHC Global Commands + */ +//! @{ + + +void flashc_no_operation(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_NOP, -1); +} + + +void flashc_erase_all(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EA, -1); +} + + +//! @} + + +/*! \name FLASHC Protection Mechanisms + */ +//! @{ + + +Bool flashc_is_security_bit_active(void) +{ + return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_SECURITY_MASK) != 0); +} + + +void flashc_activate_security_bit(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_SSB, -1); +} + + +unsigned int flashc_get_bootloader_protected_size(void) +{ + unsigned int bootprot = (1 << AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE) - 1 - + flashc_read_gp_fuse_bitfield(AVR32_FLASHC_FGPFRLO_BOOTPROT_OFFSET, + AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE); + return (bootprot) ? AVR32_FLASHC_PAGE_SIZE << bootprot : 0; +} + + +unsigned int flashc_set_bootloader_protected_size(unsigned int bootprot_size) +{ + flashc_set_gp_fuse_bitfield(AVR32_FLASHC_FGPFRLO_BOOTPROT_OFFSET, + AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE, + (1 << AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE) - 1 - + ((bootprot_size) ? + 32 - clz((((min(max(bootprot_size, AVR32_FLASHC_PAGE_SIZE << 1), + AVR32_FLASHC_PAGE_SIZE << + ((1 << AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE) - 1)) + + AVR32_FLASHC_PAGE_SIZE - 1) / + AVR32_FLASHC_PAGE_SIZE) << 1) - 1) - 1 : + 0)); + return flashc_get_bootloader_protected_size(); +} + + +Bool flashc_is_external_privileged_fetch_locked(void) +{ + return (!flashc_read_gp_fuse_bit(AVR32_FLASHC_FGPFRLO_EPFL_OFFSET)); +} + + +void flashc_lock_external_privileged_fetch(Bool lock) +{ + flashc_set_gp_fuse_bit(AVR32_FLASHC_FGPFRLO_EPFL_OFFSET, !lock); +} + + +Bool flashc_is_page_region_locked(int page_number) +{ + return flashc_is_region_locked(flashc_get_page_region(page_number)); +} + + +Bool flashc_is_region_locked(unsigned int region) +{ + return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_LOCK0_MASK << (region & (AVR32_FLASHC_REGIONS - 1))) != 0); +} + + +void flashc_lock_page_region(int page_number, Bool lock) +{ + flashc_issue_command((lock) ? AVR32_FLASHC_FCMD_CMD_LP : AVR32_FLASHC_FCMD_CMD_UP, page_number); +} + + +void flashc_lock_region(unsigned int region, Bool lock) +{ + flashc_lock_page_region(flashc_get_region_first_page_number(region), lock); +} + + +void flashc_lock_all_regions(Bool lock) +{ + unsigned int error_status = 0; + unsigned int region = AVR32_FLASHC_REGIONS; + while (region) + { + flashc_lock_region(--region, lock); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; +} + + +//! @} + + +/*! \name Access to General-Purpose Fuses + */ +//! @{ + + +Bool flashc_read_gp_fuse_bit(unsigned int gp_fuse_bit) +{ + return ((flashc_read_all_gp_fuses() & 1ULL << (gp_fuse_bit & 0x3F)) != 0); +} + + +U64 flashc_read_gp_fuse_bitfield(unsigned int pos, unsigned int width) +{ + return flashc_read_all_gp_fuses() >> (pos & 0x3F) & ((1ULL << min(width, 64)) - 1); +} + + +U8 flashc_read_gp_fuse_byte(unsigned int gp_fuse_byte) +{ + return flashc_read_all_gp_fuses() >> ((gp_fuse_byte & 0x07) << 3); +} + + +U64 flashc_read_all_gp_fuses(void) +{ + return AVR32_FLASHC.fgpfrlo | (U64)AVR32_FLASHC.fgpfrhi << 32; +} + + +Bool flashc_erase_gp_fuse_bit(unsigned int gp_fuse_bit, Bool check) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EGPB, gp_fuse_bit & 0x3F); + return (check) ? flashc_read_gp_fuse_bit(gp_fuse_bit) : TRUE; +} + + +Bool flashc_erase_gp_fuse_bitfield(unsigned int pos, unsigned int width, Bool check) +{ + unsigned int error_status = 0; + unsigned int gp_fuse_bit; + pos &= 0x3F; + width = min(width, 64); + for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++) + { + flashc_erase_gp_fuse_bit(gp_fuse_bit, FALSE); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; + return (check) ? (flashc_read_gp_fuse_bitfield(pos, width) == (1ULL << width) - 1) : TRUE; +} + + +Bool flashc_erase_gp_fuse_byte(unsigned int gp_fuse_byte, Bool check) +{ + unsigned int error_status; + unsigned int current_gp_fuse_byte; + U64 value = flashc_read_all_gp_fuses(); + flashc_erase_all_gp_fuses(FALSE); + error_status = flashc_error_status; + for (current_gp_fuse_byte = 0; current_gp_fuse_byte < 8; current_gp_fuse_byte++, value >>= 8) + { + if (current_gp_fuse_byte != gp_fuse_byte) + { + flashc_write_gp_fuse_byte(current_gp_fuse_byte, value); + error_status |= flashc_error_status; + } + } + flashc_error_status = error_status; + return (check) ? (flashc_read_gp_fuse_byte(gp_fuse_byte) == 0xFF) : TRUE; +} + + +Bool flashc_erase_all_gp_fuses(Bool check) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EAGPF, -1); + return (check) ? (flashc_read_all_gp_fuses() == 0xFFFFFFFFFFFFFFFFULL) : TRUE; +} + + +void flashc_write_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value) +{ + if (!value) + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WGPB, gp_fuse_bit & 0x3F); +} + + +void flashc_write_gp_fuse_bitfield(unsigned int pos, unsigned int width, U64 value) +{ + unsigned int error_status = 0; + unsigned int gp_fuse_bit; + pos &= 0x3F; + width = min(width, 64); + for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++, value >>= 1) + { + flashc_write_gp_fuse_bit(gp_fuse_bit, value & 0x01); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; +} + + +void flashc_write_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_PGPFB, (gp_fuse_byte & 0x07) | value << 3); +} + + +void flashc_write_all_gp_fuses(U64 value) +{ + unsigned int error_status = 0; + unsigned int gp_fuse_byte; + for (gp_fuse_byte = 0; gp_fuse_byte < 8; gp_fuse_byte++, value >>= 8) + { + flashc_write_gp_fuse_byte(gp_fuse_byte, value); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; +} + + +void flashc_set_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value) +{ + if (value) + flashc_erase_gp_fuse_bit(gp_fuse_bit, FALSE); + else + flashc_write_gp_fuse_bit(gp_fuse_bit, FALSE); +} + + +void flashc_set_gp_fuse_bitfield(unsigned int pos, unsigned int width, U64 value) +{ + unsigned int error_status = 0; + unsigned int gp_fuse_bit; + pos &= 0x3F; + width = min(width, 64); + for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++, value >>= 1) + { + flashc_set_gp_fuse_bit(gp_fuse_bit, value & 0x01); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; +} + + +void flashc_set_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value) +{ + unsigned int error_status; + switch (value) + { + case 0xFF: + flashc_erase_gp_fuse_byte(gp_fuse_byte, FALSE); + break; + case 0x00: + flashc_write_gp_fuse_byte(gp_fuse_byte, 0x00); + break; + default: + flashc_erase_gp_fuse_byte(gp_fuse_byte, FALSE); + error_status = flashc_error_status; + flashc_write_gp_fuse_byte(gp_fuse_byte, value); + flashc_error_status |= error_status; + } +} + + +void flashc_set_all_gp_fuses(U64 value) +{ + unsigned int error_status; + switch (value) + { + case 0xFFFFFFFFFFFFFFFFULL: + flashc_erase_all_gp_fuses(FALSE); + break; + case 0x0000000000000000ULL: + flashc_write_all_gp_fuses(0x0000000000000000ULL); + break; + default: + flashc_erase_all_gp_fuses(FALSE); + error_status = flashc_error_status; + flashc_write_all_gp_fuses(value); + flashc_error_status |= error_status; + } +} + + +//! @} + + +/*! \name Access to Flash Pages + */ +//! @{ + + +void flashc_clear_page_buffer(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_CPB, -1); +} + + +Bool flashc_is_page_erased(void) +{ + return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_QPRR_MASK) != 0); +} + + +Bool flashc_quick_page_read(int page_number) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_QPR, page_number); + return flashc_is_page_erased(); +} + + +Bool flashc_erase_page(int page_number, Bool check) +{ + Bool page_erased = TRUE; + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EP, page_number); + if (check) + { + unsigned int error_status = flashc_error_status; + page_erased = flashc_quick_page_read(-1); + flashc_error_status |= error_status; + } + return page_erased; +} + + +Bool flashc_erase_all_pages(Bool check) +{ + Bool all_pages_erased = TRUE; + unsigned int error_status = 0; + unsigned int page_number = flashc_get_page_count(); + while (page_number) + { + all_pages_erased &= flashc_erase_page(--page_number, check); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; + return all_pages_erased; +} + + +void flashc_write_page(int page_number) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WP, page_number); +} + + +Bool flashc_quick_user_page_read(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_QPRUP, -1); + return flashc_is_page_erased(); +} + + +Bool flashc_erase_user_page(Bool check) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EUP, -1); + return (check) ? flashc_quick_user_page_read() : TRUE; +} + + +void flashc_write_user_page(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WUP, -1); +} + + +volatile void *flashc_memset8(volatile void *dst, U8 src, size_t nbytes, Bool erase) +{ + return flashc_memset16(dst, src | (U16)src << 8, nbytes, erase); +} + + +volatile void *flashc_memset16(volatile void *dst, U16 src, size_t nbytes, Bool erase) +{ + return flashc_memset32(dst, src | (U32)src << 16, nbytes, erase); +} + + +volatile void *flashc_memset32(volatile void *dst, U32 src, size_t nbytes, Bool erase) +{ + return flashc_memset64(dst, src | (U64)src << 32, nbytes, erase); +} + + +volatile void *flashc_memset64(volatile void *dst, U64 src, size_t nbytes, Bool erase) +{ + // Use aggregated pointers to have several alignments available for a same address. + UnionCVPtr flash_array_end; + UnionVPtr dest; + Union64 source = {0}; + StructCVPtr dest_end; + UnionCVPtr flash_page_source_end; + Bool incomplete_flash_page_end; + Union64 flash_dword; + UnionVPtr tmp; + unsigned int error_status = 0; + unsigned int i; + + // Reformat arguments. + flash_array_end.u8ptr = AVR32_FLASH + flashc_get_flash_size(); + dest.u8ptr = dst; + for (i = (Get_align((U32)dest.u8ptr, sizeof(U64)) - 1) & (sizeof(U64) - 1); + src; i = (i - 1) & (sizeof(U64) - 1)) + { + source.u8[i] = src; + src >>= 8; + } + dest_end.u8ptr = dest.u8ptr + nbytes; + + // If destination is outside flash, go to next flash page if any. + if (dest.u8ptr < AVR32_FLASH) + { + dest.u8ptr = AVR32_FLASH; + } + else if (flash_array_end.u8ptr <= dest.u8ptr && dest.u8ptr < AVR32_FLASHC_USER_PAGE) + { + dest.u8ptr = AVR32_FLASHC_USER_PAGE; + } + + // If end of destination is outside flash, move it to the end of the previous flash page if any. + if (dest_end.u8ptr > AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE) + { + dest_end.u8ptr = AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE; + } + else if (AVR32_FLASHC_USER_PAGE >= dest_end.u8ptr && dest_end.u8ptr > flash_array_end.u8ptr) + { + dest_end.u8ptr = flash_array_end.u8ptr; + } + + // Align each end of destination pointer with its natural boundary. + dest_end.u16ptr = (U16 *)Align_down((U32)dest_end.u8ptr, sizeof(U16)); + dest_end.u32ptr = (U32 *)Align_down((U32)dest_end.u16ptr, sizeof(U32)); + dest_end.u64ptr = (U64 *)Align_down((U32)dest_end.u32ptr, sizeof(U64)); + + // While end of destination is not reached... + while (dest.u8ptr < dest_end.u8ptr) + { + // Clear the page buffer in order to prepare data for a flash page write. + flashc_clear_page_buffer(); + error_status |= flashc_error_status; + + // Determine where the source data will end in the current flash page. + flash_page_source_end.u64ptr = + (U64 *)min((U32)dest_end.u64ptr, + Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) + AVR32_FLASHC_PAGE_SIZE); + + // Determine if the current destination page has an incomplete end. + incomplete_flash_page_end = (Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) >= + Align_down((U32)dest_end.u8ptr, AVR32_FLASHC_PAGE_SIZE)); + + // Use a flash double-word buffer to manage unaligned accesses. + flash_dword.u64 = source.u64; + + // If destination does not point to the beginning of the current flash page... + if (!Test_align((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE)) + { + // Fill the beginning of the page buffer with the current flash page data. + // This is required by the hardware, even if page erase is not requested, + // in order to be able to write successfully to erased parts of flash + // pages that have already been written to. + for (tmp.u8ptr = (U8 *)Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE); + tmp.u64ptr < (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64)); + tmp.u64ptr++) + *tmp.u64ptr = *tmp.u64ptr; + + // If destination is not 64-bit aligned... + if (!Test_align((U32)dest.u8ptr, sizeof(U64))) + { + // Fill the beginning of the flash double-word buffer with the current + // flash page data. + // This is required by the hardware, even if page erase is not + // requested, in order to be able to write successfully to erased parts + // of flash pages that have already been written to. + for (i = 0; i < Get_align((U32)dest.u8ptr, sizeof(U64)); i++) + flash_dword.u8[i] = *tmp.u8ptr++; + + // Align the destination pointer with its 64-bit boundary. + dest.u64ptr = (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64)); + + // If the current destination double-word is not the last one... + if (dest.u64ptr < dest_end.u64ptr) + { + // Write the flash double-word buffer to the page buffer and reinitialize it. + *dest.u64ptr++ = flash_dword.u64; + flash_dword.u64 = source.u64; + } + } + } + + // Write the source data to the page buffer with 64-bit alignment. + for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--) + *dest.u64ptr++ = source.u64; + + // If the current destination page has an incomplete end... + if (incomplete_flash_page_end) + { + // This is required by the hardware, even if page erase is not requested, + // in order to be able to write successfully to erased parts of flash + // pages that have already been written to. + { + tmp.u8ptr = (volatile U8 *)dest_end.u8ptr; + + // If end of destination is not 64-bit aligned... + if (!Test_align((U32)dest_end.u8ptr, sizeof(U64))) + { + // Fill the end of the flash double-word buffer with the current flash page data. + for (i = Get_align((U32)dest_end.u8ptr, sizeof(U64)); i < sizeof(U64); i++) + flash_dword.u8[i] = *tmp.u8ptr++; + + // Write the flash double-word buffer to the page buffer. + *dest.u64ptr++ = flash_dword.u64; + } + + // Fill the end of the page buffer with the current flash page data. + for (; !Test_align((U32)tmp.u64ptr, AVR32_FLASHC_PAGE_SIZE); tmp.u64ptr++) + *tmp.u64ptr = *tmp.u64ptr; + } + } + + // If the current flash page is in the flash array... + if (dest.u8ptr <= AVR32_FLASHC_USER_PAGE) + { + // Erase the current page if requested and write it from the page buffer. + if (erase) + { + flashc_erase_page(-1, FALSE); + error_status |= flashc_error_status; + } + flashc_write_page(-1); + error_status |= flashc_error_status; + + // If the end of the flash array is reached, go to the User page. + if (dest.u8ptr >= flash_array_end.u8ptr) + dest.u8ptr = AVR32_FLASHC_USER_PAGE; + } + // If the current flash page is the User page... + else + { + // Erase the User page if requested and write it from the page buffer. + if (erase) + { + flashc_erase_user_page(FALSE); + error_status |= flashc_error_status; + } + flashc_write_user_page(); + error_status |= flashc_error_status; + } + } + + // Update the FLASHC error status. + flashc_error_status = error_status; + + // Return the initial destination pointer as the standard memset function does. + return dst; +} + + +volatile void *flashc_memcpy(volatile void *dst, const void *src, size_t nbytes, Bool erase) +{ + // Use aggregated pointers to have several alignments available for a same address. + UnionCVPtr flash_array_end; + UnionVPtr dest; + UnionCPtr source; + StructCVPtr dest_end; + UnionCVPtr flash_page_source_end; + Bool incomplete_flash_page_end; + Union64 flash_dword; + Bool flash_dword_pending = FALSE; + UnionVPtr tmp; + unsigned int error_status = 0; + unsigned int i, j; + + // Reformat arguments. + flash_array_end.u8ptr = AVR32_FLASH + flashc_get_flash_size(); + dest.u8ptr = dst; + source.u8ptr = src; + dest_end.u8ptr = dest.u8ptr + nbytes; + + // If destination is outside flash, go to next flash page if any. + if (dest.u8ptr < AVR32_FLASH) + { + source.u8ptr += AVR32_FLASH - dest.u8ptr; + dest.u8ptr = AVR32_FLASH; + } + else if (flash_array_end.u8ptr <= dest.u8ptr && dest.u8ptr < AVR32_FLASHC_USER_PAGE) + { + source.u8ptr += AVR32_FLASHC_USER_PAGE - dest.u8ptr; + dest.u8ptr = AVR32_FLASHC_USER_PAGE; + } + + // If end of destination is outside flash, move it to the end of the previous flash page if any. + if (dest_end.u8ptr > AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE) + { + dest_end.u8ptr = AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE; + } + else if (AVR32_FLASHC_USER_PAGE >= dest_end.u8ptr && dest_end.u8ptr > flash_array_end.u8ptr) + { + dest_end.u8ptr = flash_array_end.u8ptr; + } + + // Align each end of destination pointer with its natural boundary. + dest_end.u16ptr = (U16 *)Align_down((U32)dest_end.u8ptr, sizeof(U16)); + dest_end.u32ptr = (U32 *)Align_down((U32)dest_end.u16ptr, sizeof(U32)); + dest_end.u64ptr = (U64 *)Align_down((U32)dest_end.u32ptr, sizeof(U64)); + + // While end of destination is not reached... + while (dest.u8ptr < dest_end.u8ptr) + { + // Clear the page buffer in order to prepare data for a flash page write. + flashc_clear_page_buffer(); + error_status |= flashc_error_status; + + // Determine where the source data will end in the current flash page. + flash_page_source_end.u64ptr = + (U64 *)min((U32)dest_end.u64ptr, + Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) + AVR32_FLASHC_PAGE_SIZE); + + // Determine if the current destination page has an incomplete end. + incomplete_flash_page_end = (Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) >= + Align_down((U32)dest_end.u8ptr, AVR32_FLASHC_PAGE_SIZE)); + + // If destination does not point to the beginning of the current flash page... + if (!Test_align((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE)) + { + // Fill the beginning of the page buffer with the current flash page data. + // This is required by the hardware, even if page erase is not requested, + // in order to be able to write successfully to erased parts of flash + // pages that have already been written to. + for (tmp.u8ptr = (U8 *)Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE); + tmp.u64ptr < (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64)); + tmp.u64ptr++) + *tmp.u64ptr = *tmp.u64ptr; + + // If destination is not 64-bit aligned... + if (!Test_align((U32)dest.u8ptr, sizeof(U64))) + { + // Fill the beginning of the flash double-word buffer with the current + // flash page data. + // This is required by the hardware, even if page erase is not + // requested, in order to be able to write successfully to erased parts + // of flash pages that have already been written to. + for (i = 0; i < Get_align((U32)dest.u8ptr, sizeof(U64)); i++) + flash_dword.u8[i] = *tmp.u8ptr++; + + // Fill the end of the flash double-word buffer with the source data. + for (; i < sizeof(U64); i++) + flash_dword.u8[i] = *source.u8ptr++; + + // Align the destination pointer with its 64-bit boundary. + dest.u64ptr = (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64)); + + // If the current destination double-word is not the last one... + if (dest.u64ptr < dest_end.u64ptr) + { + // Write the flash double-word buffer to the page buffer. + *dest.u64ptr++ = flash_dword.u64; + } + // If the current destination double-word is the last one, the flash + // double-word buffer must be kept for later. + else flash_dword_pending = TRUE; + } + } + + // Read the source data with the maximal possible alignment and write it to + // the page buffer with 64-bit alignment. + switch (Get_align((U32)source.u8ptr, sizeof(U32))) + { + case 0: + for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--) + *dest.u64ptr++ = *source.u64ptr++; + break; + + case sizeof(U16): + for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--) + { + for (j = 0; j < sizeof(U64) / sizeof(U16); j++) flash_dword.u16[j] = *source.u16ptr++; + *dest.u64ptr++ = flash_dword.u64; + } + break; + + default: + for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--) + { + for (j = 0; j < sizeof(U64); j++) flash_dword.u8[j] = *source.u8ptr++; + *dest.u64ptr++ = flash_dword.u64; + } + } + + // If the current destination page has an incomplete end... + if (incomplete_flash_page_end) + { + // If the flash double-word buffer is in use, do not initialize it. + if (flash_dword_pending) i = Get_align((U32)dest_end.u8ptr, sizeof(U64)); + // If the flash double-word buffer is free... + else + { + // Fill the beginning of the flash double-word buffer with the source data. + for (i = 0; i < Get_align((U32)dest_end.u8ptr, sizeof(U64)); i++) + flash_dword.u8[i] = *source.u8ptr++; + } + + // This is required by the hardware, even if page erase is not requested, + // in order to be able to write successfully to erased parts of flash + // pages that have already been written to. + { + tmp.u8ptr = (volatile U8 *)dest_end.u8ptr; + + // If end of destination is not 64-bit aligned... + if (!Test_align((U32)dest_end.u8ptr, sizeof(U64))) + { + // Fill the end of the flash double-word buffer with the current flash page data. + for (; i < sizeof(U64); i++) + flash_dword.u8[i] = *tmp.u8ptr++; + + // Write the flash double-word buffer to the page buffer. + *dest.u64ptr++ = flash_dword.u64; + } + + // Fill the end of the page buffer with the current flash page data. + for (; !Test_align((U32)tmp.u64ptr, AVR32_FLASHC_PAGE_SIZE); tmp.u64ptr++) + *tmp.u64ptr = *tmp.u64ptr; + } + } + + // If the current flash page is in the flash array... + if (dest.u8ptr <= AVR32_FLASHC_USER_PAGE) + { + // Erase the current page if requested and write it from the page buffer. + if (erase) + { + flashc_erase_page(-1, FALSE); + error_status |= flashc_error_status; + } + flashc_write_page(-1); + error_status |= flashc_error_status; + + // If the end of the flash array is reached, go to the User page. + if (dest.u8ptr >= flash_array_end.u8ptr) + { + source.u8ptr += AVR32_FLASHC_USER_PAGE - dest.u8ptr; + dest.u8ptr = AVR32_FLASHC_USER_PAGE; + } + } + // If the current flash page is the User page... + else + { + // Erase the User page if requested and write it from the page buffer. + if (erase) + { + flashc_erase_user_page(FALSE); + error_status |= flashc_error_status; + } + flashc_write_user_page(); + error_status |= flashc_error_status; + } + } + + // Update the FLASHC error status. + flashc_error_status = error_status; + + // Return the initial destination pointer as the standard memcpy function does. + return dst; +} + + +#if UC3C +void flashc_set_flash_waitstate_and_readmode(unsigned long cpu_f_hz) +{ + //! Device-specific data + #undef AVR32_FLASHC_FWS_0_MAX_FREQ + #undef AVR32_FLASHC_FWS_1_MAX_FREQ + #undef AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ + #undef AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ + #define AVR32_FLASHC_FWS_0_MAX_FREQ 33000000 + #define AVR32_FLASHC_FWS_1_MAX_FREQ 66000000 + #define AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ 33000000 + #define AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ 72000000 + // These defines are missing from or wrong in the toolchain header files uc3cxxx.h + // Put a Bugzilla + + if(cpu_f_hz > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ) // > 33MHz + { + // Set a wait-state + flashc_set_wait_state(1); + if(cpu_f_hz <= AVR32_FLASHC_FWS_1_MAX_FREQ) // <= 66MHz and >33Mhz + { + // Disable the high-speed read mode. + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1); + } + else // > 66Mhz + { + // Enable the high-speed read mode. + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1); + } + } + else // <= 33 MHz + { + // Disable wait-state + flashc_set_wait_state(0); + + // Disable the high-speed read mode. + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1); + + } +} +#endif // UC3C device-specific implementation + +//! @} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC/flashc.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC/flashc.h new file mode 100644 index 0000000..9f2547a --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC/flashc.h @@ -0,0 +1,1002 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FLASHC driver for AVR32 UC3. + * + * AVR32 Flash Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a FLASHC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _FLASHC_H_ +#define _FLASHC_H_ + +#include <avr32/io.h> +#include <stddef.h> +#include "compiler.h" + +//! Number of flash regions defined by the FLASHC. +#define AVR32_FLASHC_REGIONS (AVR32_FLASHC_FLASH_SIZE /\ + (AVR32_FLASHC_PAGES_PR_REGION * AVR32_FLASHC_PAGE_SIZE)) + + +/*! \name Flash Properties + */ +//! @{ + +/*! \brief Gets the size of the whole flash array. + * + * \return The size of the whole flash array in bytes. + */ +extern unsigned int flashc_get_flash_size(void); + +/*! \brief Gets the total number of pages in the flash array. + * + * \return The total number of pages in the flash array. + */ +extern unsigned int flashc_get_page_count(void); + +/*! \brief Gets the number of pages in each flash region. + * + * \return The number of pages in each flash region. + */ +extern unsigned int flashc_get_page_count_per_region(void); + +/*! \brief Gets the region number of a page. + * + * \param page_number The page number: + * \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within + * the flash array; + * \arg <tt>< 0</tt>: the current page number. + * + * \return The region number of the specified page. + */ +extern unsigned int flashc_get_page_region(int page_number); + +/*! \brief Gets the number of the first page of a region. + * + * \param region The region number: \c 0 to <tt>(AVR32_FLASHC_REGIONS - 1)</tt>. + * + * \return The number of the first page of the specified region. + */ +extern unsigned int flashc_get_region_first_page_number(unsigned int region); + +//! @} + + +/*! \name FLASHC Control + */ +//! @{ + +/*! \brief Gets the number of wait states of flash read accesses. + * + * \return The number of wait states of flash read accesses. + */ +extern unsigned int flashc_get_wait_state(void); + +/*! \brief Sets the number of wait states of flash read accesses. + * + * \param wait_state The number of wait states of flash read accesses: \c 0 to + * \c 1. + */ +extern void flashc_set_wait_state(unsigned int wait_state); + +/*! \brief Tells whether the Flash Ready interrupt is enabled. + * + * \return Whether the Flash Ready interrupt is enabled. + */ +extern Bool flashc_is_ready_int_enabled(void); + +/*! \brief Enables or disables the Flash Ready interrupt. + * + * \param enable Whether to enable the Flash Ready interrupt: \c TRUE or + * \c FALSE. + */ +extern void flashc_enable_ready_int(Bool enable); + +/*! \brief Tells whether the Lock Error interrupt is enabled. + * + * \return Whether the Lock Error interrupt is enabled. + */ +extern Bool flashc_is_lock_error_int_enabled(void); + +/*! \brief Enables or disables the Lock Error interrupt. + * + * \param enable Whether to enable the Lock Error interrupt: \c TRUE or + * \c FALSE. + */ +extern void flashc_enable_lock_error_int(Bool enable); + +/*! \brief Tells whether the Programming Error interrupt is enabled. + * + * \return Whether the Programming Error interrupt is enabled. + */ +extern Bool flashc_is_prog_error_int_enabled(void); + +/*! \brief Enables or disables the Programming Error interrupt. + * + * \param enable Whether to enable the Programming Error interrupt: \c TRUE or + * \c FALSE. + */ +extern void flashc_enable_prog_error_int(Bool enable); + +//! @} + + +/*! \name FLASHC Status + */ +//! @{ + +/*! \brief Tells whether the FLASHC is ready to run a new command. + * + * \return Whether the FLASHC is ready to run a new command. + */ +extern Bool flashc_is_ready(void); + +/*! \brief Waits actively until the FLASHC is ready to run a new command. + * + * This is the default function assigned to \ref flashc_wait_until_ready. + */ +extern void flashc_default_wait_until_ready(void); + +//! Pointer to the function used by the driver when it needs to wait until the +//! FLASHC is ready to run a new command. +//! The default function is \ref flashc_default_wait_until_ready. +//! The user may change this pointer to use another implementation. +extern void (*volatile flashc_wait_until_ready)(void); + +/*! \brief Tells whether a Lock Error has occurred during the last function + * called that issued one or more FLASHC commands. + * + * \return Whether a Lock Error has occurred during the last function called + * that issued one or more FLASHC commands. + */ +extern Bool flashc_is_lock_error(void); + +/*! \brief Tells whether a Programming Error has occurred during the last + * function called that issued one or more FLASHC commands. + * + * \return Whether a Programming Error has occurred during the last function + * called that issued one or more FLASHC commands. + */ +extern Bool flashc_is_programming_error(void); + +//! @} + + +/*! \name FLASHC Command Control + */ +//! @{ + +/*! \brief Gets the last issued FLASHC command. + * + * \return The last issued FLASHC command. + */ +extern unsigned int flashc_get_command(void); + +/*! \brief Gets the current FLASHC page number. + * + * \return The current FLASHC page number. + */ +extern unsigned int flashc_get_page_number(void); + +/*! \brief Issues a FLASHC command. + * + * \param command The command: \c AVR32_FLASHC_FCMD_CMD_x. + * \param page_number The page number to apply the command to: + * \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within + * the flash array; + * \arg <tt>< 0</tt>: use this to apply the command to the current page number + * or if the command does not apply to any page number; + * \arg this argument may have other meanings according to the command. See + * the FLASHC chapter of the MCU datasheet. + * + * \warning A Lock Error is issued if the command violates the protection + * mechanism. + * + * \warning A Programming Error is issued if the command is invalid. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_issue_command(unsigned int command, int page_number); + +//! @} + + +/*! \name FLASHC Global Commands + */ +//! @{ + +/*! \brief Issues a No Operation command to the FLASHC. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_no_operation(void); + +/*! \brief Issues an Erase All command to the FLASHC. + * + * This command erases all bits in the flash array, the general-purpose fuse + * bits and the Security bit. The User page is not erased. + * + * This command also ensures that all volatile memories, such as register file + * and RAMs, are erased before the Security bit is erased, i.e. deactivated. + * + * \warning A Lock Error is issued if at least one region is locked or the + * bootloader protection is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern void flashc_erase_all(void); + +//! @} + + +/*! \name FLASHC Protection Mechanisms + */ +//! @{ + +/*! \brief Tells whether the Security bit is active. + * + * \return Whether the Security bit is active. + */ +extern Bool flashc_is_security_bit_active(void); + +/*! \brief Activates the Security bit. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_activate_security_bit(void); + +/*! \brief Gets the bootloader protected size. + * + * \return The bootloader protected size in bytes. + */ +extern unsigned int flashc_get_bootloader_protected_size(void); + +/*! \brief Sets the bootloader protected size. + * + * \param bootprot_size The wanted bootloader protected size in bytes. If this + * size is not supported, the actual size will be the + * nearest greater available size or the maximal possible + * size if the requested size is too large. + * + * \return The actual bootloader protected size in bytes. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern unsigned int flashc_set_bootloader_protected_size(unsigned int bootprot_size); + +/*! \brief Tells whether external privileged fetch is locked. + * + * \return Whether external privileged fetch is locked. + */ +extern Bool flashc_is_external_privileged_fetch_locked(void); + +/*! \brief Locks or unlocks external privileged fetch. + * + * \param lock Whether to lock external privileged fetch: \c TRUE or \c FALSE. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_lock_external_privileged_fetch(Bool lock); + +/*! \brief Tells whether the region of a page is locked. + * + * \param page_number The page number: + * \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within + * the flash array; + * \arg <tt>< 0</tt>: the current page number. + * + * \return Whether the region of the specified page is locked. + */ +extern Bool flashc_is_page_region_locked(int page_number); + +/*! \brief Tells whether a region is locked. + * + * \param region The region number: \c 0 to <tt>(AVR32_FLASHC_REGIONS - 1)</tt>. + * + * \return Whether the specified region is locked. + */ +extern Bool flashc_is_region_locked(unsigned int region); + +/*! \brief Locks or unlocks the region of a page. + * + * \param page_number The page number: + * \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within + * the flash array; + * \arg <tt>< 0</tt>: the current page number. + * \param lock Whether to lock the region of the specified page: \c TRUE or + * \c FALSE. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_lock_page_region(int page_number, Bool lock); + +/*! \brief Locks or unlocks a region. + * + * \param region The region number: \c 0 to <tt>(AVR32_FLASHC_REGIONS - 1)</tt>. + * \param lock Whether to lock the specified region: \c TRUE or \c FALSE. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_lock_region(unsigned int region, Bool lock); + +/*! \brief Locks or unlocks all regions. + * + * \param lock Whether to lock the regions: \c TRUE or \c FALSE. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_lock_all_regions(Bool lock); + +//! @} + + +/*! \name Access to General-Purpose Fuses + */ +//! @{ + +/*! \brief Reads a general-purpose fuse bit. + * + * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 63. + * + * \return The value of the specified general-purpose fuse bit. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern Bool flashc_read_gp_fuse_bit(unsigned int gp_fuse_bit); + +/*! \brief Reads a general-purpose fuse bit-field. + * + * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to + * \c 63. + * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to + * \c 64. + * + * \return The value of the specified general-purpose fuse bit-field. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern U64 flashc_read_gp_fuse_bitfield(unsigned int pos, unsigned int width); + +/*! \brief Reads a general-purpose fuse byte. + * + * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 7. + * + * \return The value of the specified general-purpose fuse byte. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern U8 flashc_read_gp_fuse_byte(unsigned int gp_fuse_byte); + +/*! \brief Reads all general-purpose fuses. + * + * \return The value of all general-purpose fuses as a word. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern U64 flashc_read_all_gp_fuses(void); + +/*! \brief Erases a general-purpose fuse bit. + * + * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 63. + * \param check Whether to check erase: \c TRUE or \c FALSE. + * + * \return Whether the erase succeeded or always \c TRUE if erase check was not + * requested. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern Bool flashc_erase_gp_fuse_bit(unsigned int gp_fuse_bit, Bool check); + +/*! \brief Erases a general-purpose fuse bit-field. + * + * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to + * \c 63. + * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to + * \c 64. + * \param check Whether to check erase: \c TRUE or \c FALSE. + * + * \return Whether the erase succeeded or always \c TRUE if erase check was not + * requested. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern Bool flashc_erase_gp_fuse_bitfield(unsigned int pos, unsigned int width, Bool check); + +/*! \brief Erases a general-purpose fuse byte. + * + * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 7. + * \param check Whether to check erase: \c TRUE or \c FALSE. + * + * \return Whether the erase succeeded or always \c TRUE if erase check was not + * requested. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern Bool flashc_erase_gp_fuse_byte(unsigned int gp_fuse_byte, Bool check); + +/*! \brief Erases all general-purpose fuses. + * + * \param check Whether to check erase: \c TRUE or \c FALSE. + * + * \return Whether the erase succeeded or always \c TRUE if erase check was not + * requested. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern Bool flashc_erase_all_gp_fuses(Bool check); + +/*! \brief Writes a general-purpose fuse bit. + * + * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 63. + * \param value The value of the specified general-purpose fuse bit. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_write_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value); + +/*! \brief Writes a general-purpose fuse bit-field. + * + * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to + * \c 63. + * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to + * \c 64. + * \param value The value of the specified general-purpose fuse bit-field. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_write_gp_fuse_bitfield(unsigned int pos, unsigned int width, U64 value); + +/*! \brief Writes a general-purpose fuse byte. + * + * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 7. + * \param value The value of the specified general-purpose fuse byte. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_write_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value); + +/*! \brief Writes all general-purpose fuses. + * + * \param value The value of all general-purpose fuses as a word. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_write_all_gp_fuses(U64 value); + +/*! \brief Sets a general-purpose fuse bit with the appropriate erase and write + * operations. + * + * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 63. + * \param value The value of the specified general-purpose fuse bit. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_set_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value); + +/*! \brief Sets a general-purpose fuse bit-field with the appropriate erase and + * write operations. + * + * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to + * \c 63. + * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to + * \c 64. + * \param value The value of the specified general-purpose fuse bit-field. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_set_gp_fuse_bitfield(unsigned int pos, unsigned int width, U64 value); + +/*! \brief Sets a general-purpose fuse byte with the appropriate erase and write + * operations. + * + * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 7. + * \param value The value of the specified general-purpose fuse byte. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_set_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value); + +/*! \brief Sets all general-purpose fuses with the appropriate erase and write + * operations. + * + * \param value The value of all general-purpose fuses as a word. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_set_all_gp_fuses(U64 value); + +//! @} + + +/*! \name Access to Flash Pages + */ +//! @{ + +/*! \brief Clears the page buffer. + * + * This command resets all bits in the page buffer to one. Write accesses to the + * page buffer can only change page buffer bits from one to zero. + * + * \warning The page buffer is not automatically reset after a page write. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_clear_page_buffer(void); + +/*! \brief Tells whether the page to which the last Quick Page Read or Quick + * Page Read User Page command was applied was erased. + * + * \return Whether the page to which the last Quick Page Read or Quick Page Read + * User Page command was applied was erased. + */ +extern Bool flashc_is_page_erased(void); + +/*! \brief Applies the Quick Page Read command to a page. + * + * \param page_number The page number: + * \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within + * the flash array; + * \arg <tt>< 0</tt>: the current page number. + * + * \return Whether the specified page is erased. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern Bool flashc_quick_page_read(int page_number); + +/*! \brief Erases a page. + * + * \param page_number The page number: + * \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within + * the flash array; + * \arg <tt>< 0</tt>: the current page number. + * \param check Whether to check erase: \c TRUE or \c FALSE. + * + * \return Whether the erase succeeded or always \c TRUE if erase check was not + * requested. + * + * \warning A Lock Error is issued if the command is applied to a page belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern Bool flashc_erase_page(int page_number, Bool check); + +/*! \brief Erases all pages within the flash array. + * + * \param check Whether to check erase: \c TRUE or \c FALSE. + * + * \return Whether the erase succeeded or always \c TRUE if erase check was not + * requested. + * + * \warning A Lock Error is issued if at least one region is locked or the + * bootloader protection is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern Bool flashc_erase_all_pages(Bool check); + +/*! \brief Writes a page from the page buffer. + * + * \param page_number The page number: + * \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within + * the flash array; + * \arg <tt>< 0</tt>: the current page number. + * + * \warning A Lock Error is issued if the command is applied to a page belonging + * to a locked region or to the bootloader protected area. + * + * \warning The page buffer is not automatically reset after a page write. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits. + */ +extern void flashc_write_page(int page_number); + +/*! \brief Issues a Quick Page Read User Page command to the FLASHC. + * + * \return Whether the User page is erased. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern Bool flashc_quick_user_page_read(void); + +/*! \brief Erases the User page. + * + * \param check Whether to check erase: \c TRUE or \c FALSE. + * + * \return Whether the erase succeeded or always \c TRUE if erase check was not + * requested. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern Bool flashc_erase_user_page(Bool check); + +/*! \brief Writes the User page from the page buffer. + * + * \warning The page buffer is not automatically reset after a page write. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits. + */ +extern void flashc_write_user_page(void); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src source byte. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source byte. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c TRUE or \c FALSE. + * + * \return The value of \a dst. + * + * \warning This function may be called with \a erase set to \c FALSE only if + * the destination consists only of erased words, i.e. this function + * can not be used to write only one bit of a previously written word. + * E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the + * resulting value in flash may be different from \c 0x00000000. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memset8(volatile void *dst, U8 src, size_t nbytes, Bool erase); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src big-endian source half-word. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source half-word. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c TRUE or \c FALSE. + * + * \return The value of \a dst. + * + * \warning This function may be called with \a erase set to \c FALSE only if + * the destination consists only of erased words, i.e. this function + * can not be used to write only one bit of a previously written word. + * E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the + * resulting value in flash may be different from \c 0x00000000. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memset16(volatile void *dst, U16 src, size_t nbytes, Bool erase); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src big-endian source word. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source word. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c TRUE or \c FALSE. + * + * \return The value of \a dst. + * + * \warning This function may be called with \a erase set to \c FALSE only if + * the destination consists only of erased words, i.e. this function + * can not be used to write only one bit of a previously written word. + * E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the + * resulting value in flash may be different from \c 0x00000000. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memset32(volatile void *dst, U32 src, size_t nbytes, Bool erase); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src big-endian source double-word. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source double-word. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c TRUE or \c FALSE. + * + * \return The value of \a dst. + * + * \warning This function may be called with \a erase set to \c FALSE only if + * the destination consists only of erased words, i.e. this function + * can not be used to write only one bit of a previously written word. + * E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the + * resulting value in flash may be different from \c 0x00000000. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memset64(volatile void *dst, U64 src, size_t nbytes, Bool erase); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src big-endian source pattern. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source double-word. + * \param src_width \a src width in bits: 8, 16, 32 or 64. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c TRUE or \c FALSE. + * + * \return The value of \a dst. + * + * \warning This function may be called with \a erase set to \c FALSE only if + * the destination consists only of erased words, i.e. this function + * can not be used to write only one bit of a previously written word. + * E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the + * resulting value in flash may be different from \c 0x00000000. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +#define flashc_memset(dst, src, src_width, nbytes, erase) \ + TPASTE2(flashc_memset, src_width)((dst), (src), (nbytes), (erase)) + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the source pointed to by \a src. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Pointer to source data. + * \param nbytes Number of bytes to copy. + * \param erase Whether to erase before writing: \c TRUE or \c FALSE. + * + * \return The value of \a dst. + * + * \warning If copying takes place between areas that overlap, the behavior is + * undefined. + * + * \warning This function may be called with \a erase set to \c FALSE only if + * the destination consists only of erased words, i.e. this function + * can not be used to write only one bit of a previously written word. + * E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the + * resulting value in flash may be different from \c 0x00000000. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memcpy(volatile void *dst, const void *src, size_t nbytes, Bool erase); + +#if UC3C + +/*! \brief Depednding to the CPU frequency, set the wait states of flash read + * accesses and enable or disable the High speed read mode. + * + * \param cpu_f_hz The CPU frequency + */ +void flashc_set_flash_waitstate_and_readmode(unsigned long cpu_f_hz); +#endif // UC3C device-specific implementation + +//! @} + + +#endif // _FLASHC_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO/gpio.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO/gpio.c new file mode 100644 index 0000000..b6b83c7 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO/gpio.c @@ -0,0 +1,458 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief GPIO driver for AVR32 UC3. + * + * This file defines a useful set of functions for the GPIO. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a GPIO module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include "gpio.h" + +//! GPIO module instance. +#define GPIO AVR32_GPIO + + +/*! \name Peripheral Bus Interface + */ +//! @{ + + +int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size) +{ + int status = GPIO_SUCCESS; + unsigned int i; + + for (i = 0; i < size; i++) + { + status |= gpio_enable_module_pin(gpiomap->pin, gpiomap->function); + gpiomap++; + } + + return status; +} + + +int gpio_enable_module_pin(unsigned int pin, unsigned int function) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + // Enable the correct function. + switch (function) + { + case 0: // A function. + gpio_port->pmr0c = 1 << (pin & 0x1F); + gpio_port->pmr1c = 1 << (pin & 0x1F); +#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED) + gpio_port->pmr2c = 1 << (pin & 0x1F); +#endif + break; + + case 1: // B function. + gpio_port->pmr0s = 1 << (pin & 0x1F); + gpio_port->pmr1c = 1 << (pin & 0x1F); +#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED) + gpio_port->pmr2c = 1 << (pin & 0x1F); +#endif + break; + + case 2: // C function. + gpio_port->pmr0c = 1 << (pin & 0x1F); + gpio_port->pmr1s = 1 << (pin & 0x1F); +#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED) + gpio_port->pmr2c = 1 << (pin & 0x1F); +#endif + break; + + case 3: // D function. + gpio_port->pmr0s = 1 << (pin & 0x1F); + gpio_port->pmr1s = 1 << (pin & 0x1F); +#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED) + gpio_port->pmr2c = 1 << (pin & 0x1F); +#endif + break; + +#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED) + case 4: // E function. + gpio_port->pmr0c = 1 << (pin & 0x1F); + gpio_port->pmr1c = 1 << (pin & 0x1F); + gpio_port->pmr2s = 1 << (pin & 0x1F); + break; + + case 5: // F function. + gpio_port->pmr0s = 1 << (pin & 0x1F); + gpio_port->pmr1c = 1 << (pin & 0x1F); + gpio_port->pmr2s = 1 << (pin & 0x1F); + break; + + case 6: // G function. + gpio_port->pmr0c = 1 << (pin & 0x1F); + gpio_port->pmr1s = 1 << (pin & 0x1F); + gpio_port->pmr2s = 1 << (pin & 0x1F); + break; + + case 7: // H function. + gpio_port->pmr0s = 1 << (pin & 0x1F); + gpio_port->pmr1s = 1 << (pin & 0x1F); + gpio_port->pmr2s = 1 << (pin & 0x1F); + break; +#endif + + default: + return GPIO_INVALID_ARGUMENT; + } + + // Disable GPIO control. + gpio_port->gperc = 1 << (pin & 0x1F); + + return GPIO_SUCCESS; +} + + +void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size) +{ + unsigned int i; + + for (i = 0; i < size; i++) + { + gpio_enable_gpio_pin(gpiomap->pin); + gpiomap++; + } +} + + +void gpio_enable_gpio_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->oderc = 1 << (pin & 0x1F); + gpio_port->gpers = 1 << (pin & 0x1F); +} + + +// The open-drain mode is not synthesized on the current AVR32 products. +// If one day some AVR32 products have this feature, the corresponding part +// numbers should be listed in the #if below. +// Note that other functions are available in this driver to use pins with open +// drain in GPIO mode. The advantage of the open-drain mode functions over these +// other functions is that they can be used not only in GPIO mode but also in +// module mode. +#if 0 + + +void gpio_enable_pin_open_drain(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->odmers = 1 << (pin & 0x1F); +} + + +void gpio_disable_pin_open_drain(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->odmerc = 1 << (pin & 0x1F); +} + + +#endif + + +void gpio_enable_pin_pull_up(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->puers = 1 << (pin & 0x1F); +#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED) + gpio_port->pderc = 1 << (pin & 0x1F); +#endif +} + + +void gpio_disable_pin_pull_up(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->puerc = 1 << (pin & 0x1F); +} + +#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED) +// Added support of Pull-up Resistor, Pull-down Resistor and Buskeeper Control. + +/*! \brief Enables the pull-down resistor of a pin. + * + * \param pin The pin number. + */ +void gpio_enable_pin_pull_down(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->puerc = 1 << (pin & 0x1F); + gpio_port->pders = 1 << (pin & 0x1F); +} + +/*! \brief Disables the pull-down resistor of a pin. + * + * \param pin The pin number. + */ +void gpio_disable_pin_pull_down(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->pderc = 1 << (pin & 0x1F); +} + +/*! \brief Enables the buskeeper functionality on a pin. + * + * \param pin The pin number. + */ +void gpio_enable_pin_buskeeper(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->puers = 1 << (pin & 0x1F); + gpio_port->pders = 1 << (pin & 0x1F); +} + +/*! \brief Disables the buskeeper functionality on a pin. + * + * \param pin The pin number. + */ +void gpio_disable_pin_buskeeper(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->puerc = 1 << (pin & 0x1F); + gpio_port->pderc = 1 << (pin & 0x1F); +} + +#endif + +int gpio_get_pin_value(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + return (gpio_port->pvr >> (pin & 0x1F)) & 1; +} + + +int gpio_get_gpio_pin_output_value(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + return (gpio_port->ovr >> (pin & 0x1F)) & 1; +} + + +int gpio_get_gpio_open_drain_pin_output_value(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + return ((gpio_port->oder >> (pin & 0x1F)) & 1) ^ 1; +} + + +void gpio_set_gpio_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->ovrs = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 1. + gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_clr_gpio_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0. + gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_tgl_gpio_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->ovrt = 1 << (pin & 0x1F); // Toggle the I/O line. + gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_set_gpio_open_drain_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->oderc = 1 << (pin & 0x1F); // The GPIO output driver is disabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_clr_gpio_open_drain_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0. + gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_tgl_gpio_open_drain_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line if the GPIO output driver is enabled: 0. + gpio_port->odert = 1 << (pin & 0x1F); // The GPIO output driver is toggled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_enable_pin_glitch_filter(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->gfers = 1 << (pin & 0x1F); +} + + +void gpio_disable_pin_glitch_filter(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->gferc = 1 << (pin & 0x1F); +} + +/*! \brief Configure the edge detector of an input pin + * + * \param pin The pin number. + * \param mode The edge detection mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE + * or \ref GPIO_FALLING_EDGE). + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +static int gpio_configure_edge_detector(unsigned int pin, unsigned int mode) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + // Configure the edge detector. + switch (mode) + { + case GPIO_PIN_CHANGE: + gpio_port->imr0c = 1 << (pin & 0x1F); + gpio_port->imr1c = 1 << (pin & 0x1F); + break; + + case GPIO_RISING_EDGE: + gpio_port->imr0s = 1 << (pin & 0x1F); + gpio_port->imr1c = 1 << (pin & 0x1F); + break; + + case GPIO_FALLING_EDGE: + gpio_port->imr0c = 1 << (pin & 0x1F); + gpio_port->imr1s = 1 << (pin & 0x1F); + break; + + default: + return GPIO_INVALID_ARGUMENT; + } + + return GPIO_SUCCESS; +} + + +int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + // Enable the glitch filter. + gpio_port->gfers = 1 << (pin & 0x1F); + + // Configure the edge detector. + if(GPIO_INVALID_ARGUMENT == gpio_configure_edge_detector(pin, mode)) + return(GPIO_INVALID_ARGUMENT); + + // Enable interrupt. + gpio_port->iers = 1 << (pin & 0x1F); + + return GPIO_SUCCESS; +} + + +void gpio_disable_pin_interrupt(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->ierc = 1 << (pin & 0x1F); +} + + +int gpio_get_pin_interrupt_flag(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + return (gpio_port->ifr >> (pin & 0x1F)) & 1; +} + + +void gpio_clear_pin_interrupt_flag(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->ifrc = 1 << (pin & 0x1F); +} + + +//# +//# Peripheral Event System Support. +//# +#if UC3L +int gpio_configure_pin_periph_event_mode(unsigned int pin, unsigned int mode, unsigned int use_igf) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + if(TRUE == use_igf) + { + // Enable the glitch filter. + gpio_port->gfers = 1 << (pin & 0x1F); + } + else + { + // Disable the glitch filter. + gpio_port->gferc = 1 << (pin & 0x1F); + } + + // Configure the edge detector. + return(gpio_configure_edge_detector(pin, mode)); +} + +#endif + +//! @} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO/gpio.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO/gpio.h new file mode 100644 index 0000000..f0b5fd8 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO/gpio.h @@ -0,0 +1,583 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief GPIO header for AVR32 UC3. + * + * This file contains basic GPIO driver functions. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a GPIO module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#include <avr32/io.h> +#include "compiler.h" + +/*! \name Return Values of the GPIO API + */ +//! @{ +#define GPIO_SUCCESS 0 //!< Function successfully completed. +#define GPIO_INVALID_ARGUMENT 1 //!< Input parameters are out of range. +//! @} + + +/*! \name Interrupt Trigger Modes + */ +//! @{ +#define GPIO_PIN_CHANGE 0 //!< Interrupt triggered upon pin change. +#define GPIO_RISING_EDGE 1 //!< Interrupt triggered upon rising edge. +#define GPIO_FALLING_EDGE 2 //!< Interrupt triggered upon falling edge. +//! @} + + +//! A type definition of pins and modules connectivity. +typedef struct +{ + unsigned char pin; //!< Module pin. + unsigned char function; //!< Module function. +} gpio_map_t[]; + + +/*! \name Peripheral Bus Interface + * + * Low-speed interface with a non-deterministic number of clock cycles per + * access. + * + * This interface operates with lower clock frequencies (fPB <= fCPU), and its + * timing is not deterministic since it needs to access a shared bus which may + * be heavily loaded. + * + * \note This interface is immediately available without initialization. + */ +//! @{ + +/*! \brief Enables specific module modes for a set of pins. + * + * \param gpiomap The pin map. + * \param size The number of pins in \a gpiomap. + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +extern int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size); + +/*! \brief Enables a specific module mode for a pin. + * + * \param pin The pin number.\n + * Refer to the product header file `uc3x.h' (where x is the part + * number; e.g. x = a0512) for module pins. E.g., to enable a PWM + * channel output, the pin number can be AVR32_PWM_3_PIN for PWM + * channel 3. + * \param function The pin function.\n + * Refer to the product header file `uc3x.h' (where x is the + * part number; e.g. x = a0512) for module pin functions. E.g., + * to enable a PWM channel output, the pin function can be + * AVR32_PWM_3_FUNCTION for PWM channel 3. + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +extern int gpio_enable_module_pin(unsigned int pin, unsigned int function); + +/*! \brief Enables the GPIO mode of a set of pins. + * + * \param gpiomap The pin map. + * \param size The number of pins in \a gpiomap. + */ +extern void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size); + +/*! \brief Enables the GPIO mode of a pin. + * + * \param pin The pin number.\n + * Refer to the product header file `uc3x.h' (where x is the part + * number; e.g. x = a0512) for pin definitions. E.g., to enable the + * GPIO mode of PX21, AVR32_PIN_PX21 can be used. Module pins such as + * AVR32_PWM_3_PIN for PWM channel 3 can also be used to release + * module pins for GPIO. + */ +extern void gpio_enable_gpio_pin(unsigned int pin); + +// The open-drain mode is not synthesized on the current AVR32 products. +// If one day some AVR32 products have this feature, the corresponding part +// numbers should be listed in the #if below. +// Note that other functions are available in this driver to use pins with open +// drain in GPIO mode. The advantage of the open-drain mode functions over these +// other functions is that they can be used not only in GPIO mode but also in +// module mode. +#if 0 + +/*! \brief Enables the open-drain mode of a pin. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_open_drain(unsigned int pin); + +/*! \brief Disables the open-drain mode of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_open_drain(unsigned int pin); + +#endif + +/*! \brief Enables the pull-up resistor of a pin. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_pull_up(unsigned int pin); + +/*! \brief Disables the pull-up resistor of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_pull_up(unsigned int pin); + +#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED) +// Added support of Pull-up Resistor, Pull-down Resistor and Buskeeper Control. + +/*! \brief Enables the pull-down resistor of a pin. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_pull_down(unsigned int pin); + +/*! \brief Disables the pull-down resistor of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_pull_down(unsigned int pin); + +/*! \brief Enables the buskeeper functionality on a pin. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_buskeeper(unsigned int pin); + +/*! \brief Disables the buskeeper functionality on a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_buskeeper(unsigned int pin); + +#endif + +/*! \brief Returns the value of a pin. + * + * \param pin The pin number. + * + * \return The pin value. + */ +extern int gpio_get_pin_value(unsigned int pin); + +/*! \brief Returns the output value set for a GPIO pin. + * + * \param pin The pin number. + * + * \return The pin output value. + * + * \note This function must be used in conjunction with \ref gpio_set_gpio_pin, + * \ref gpio_clr_gpio_pin and \ref gpio_tgl_gpio_pin. + */ +extern int gpio_get_gpio_pin_output_value(unsigned int pin); + +/*! \brief Returns the output value set for a GPIO pin using open drain. + * + * \param pin The pin number. + * + * \return The pin output value. + * + * \note This function must be used in conjunction with + * \ref gpio_set_gpio_open_drain_pin, \ref gpio_clr_gpio_open_drain_pin + * and \ref gpio_tgl_gpio_open_drain_pin. + */ +extern int gpio_get_gpio_open_drain_pin_output_value(unsigned int pin); + +/*! \brief Drives a GPIO pin to 1. + * + * \param pin The pin number. + */ +extern void gpio_set_gpio_pin(unsigned int pin); + +/*! \brief Drives a GPIO pin to 0. + * + * \param pin The pin number. + */ +extern void gpio_clr_gpio_pin(unsigned int pin); + +/*! \brief Toggles a GPIO pin. + * + * \param pin The pin number. + */ +extern void gpio_tgl_gpio_pin(unsigned int pin); + +/*! \brief Drives a GPIO pin to 1 using open drain. + * + * \param pin The pin number. + */ +extern void gpio_set_gpio_open_drain_pin(unsigned int pin); + +/*! \brief Drives a GPIO pin to 0 using open drain. + * + * \param pin The pin number. + */ +extern void gpio_clr_gpio_open_drain_pin(unsigned int pin); + +/*! \brief Toggles a GPIO pin using open drain. + * + * \param pin The pin number. + */ +extern void gpio_tgl_gpio_open_drain_pin(unsigned int pin); + +/*! \brief Enables the glitch filter of a pin. + * + * When the glitch filter is enabled, a glitch with duration of less than 1 + * clock cycle is automatically rejected, while a pulse with duration of 2 clock + * cycles or more is accepted. For pulse durations between 1 clock cycle and 2 + * clock cycles, the pulse may or may not be taken into account, depending on + * the precise timing of its occurrence. Thus for a pulse to be guaranteed + * visible it must exceed 2 clock cycles, whereas for a glitch to be reliably + * filtered out, its duration must not exceed 1 clock cycle. The filter + * introduces 2 clock cycles latency. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_glitch_filter(unsigned int pin); + +/*! \brief Disables the glitch filter of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_glitch_filter(unsigned int pin); + +/*! \brief Enables the interrupt of a pin with the specified settings. + * + * \param pin The pin number. + * \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or + * \ref GPIO_FALLING_EDGE). + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +extern int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode); + +/*! \brief Disables the interrupt of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_interrupt(unsigned int pin); + +/*! \brief Gets the interrupt flag of a pin. + * + * \param pin The pin number. + * + * \return The pin interrupt flag. + */ +extern int gpio_get_pin_interrupt_flag(unsigned int pin); + +/*! \brief Clears the interrupt flag of a pin. + * + * \param pin The pin number. + */ +extern void gpio_clear_pin_interrupt_flag(unsigned int pin); + +//! @} + + +#if (defined AVR32_GPIO_LOCAL_ADDRESS) +/*! \name Local Bus Interface + * + * High-speed interface with only one clock cycle per access. + * + * This interface operates with high clock frequency (fCPU), and its timing is + * deterministic since it does not need to access a shared bus which may be + * heavily loaded. + * + * \warning To use this interface, the clock frequency of the peripheral bus on + * which the GPIO peripheral is connected must be set to the CPU clock + * frequency (fPB = fCPU). + * + * \note This interface has to be initialized in order to be available. + */ +//! @{ + +/*! \brief Enables the local bus interface for GPIO. + * + * \note This function must have been called at least once before using other + * functions in this interface. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void gpio_local_init(void) +{ + Set_system_register(AVR32_CPUCR, + Get_system_register(AVR32_CPUCR) | AVR32_CPUCR_LOCEN_MASK); +} + +/*! \brief Enables the output driver of a pin. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init must have been called beforehand. + * + * \note This function does not enable the GPIO mode of the pin. + * \ref gpio_enable_gpio_pin can be called for this purpose. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void gpio_local_enable_pin_output_driver(unsigned int pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F); +} + +/*! \brief Disables the output driver of a pin. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init must have been called beforehand. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void gpio_local_disable_pin_output_driver(unsigned int pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F); +} + +/*! \brief Returns the value of a pin. + * + * \param pin The pin number. + * + * \return The pin value. + * + * \note \ref gpio_local_init must have been called beforehand. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ int gpio_local_get_pin_value(unsigned int pin) +{ + return (AVR32_GPIO_LOCAL.port[pin >> 5].pvr >> (pin & 0x1F)) & 1; +} + +/*! \brief Drives a GPIO pin to 1. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init must have been called beforehand. + * + * \note This function does not enable the GPIO mode of the pin nor its output + * driver. \ref gpio_enable_gpio_pin and + * \ref gpio_local_enable_pin_output_driver can be called for this + * purpose. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void gpio_local_set_gpio_pin(unsigned int pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].ovrs = 1 << (pin & 0x1F); +} + +/*! \brief Drives a GPIO pin to 0. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init must have been called beforehand. + * + * \note This function does not enable the GPIO mode of the pin nor its output + * driver. \ref gpio_enable_gpio_pin and + * \ref gpio_local_enable_pin_output_driver can be called for this + * purpose. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void gpio_local_clr_gpio_pin(unsigned int pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F); +} + +/*! \brief Toggles a GPIO pin. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init must have been called beforehand. + * + * \note This function does not enable the GPIO mode of the pin nor its output + * driver. \ref gpio_enable_gpio_pin and + * \ref gpio_local_enable_pin_output_driver can be called for this + * purpose. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void gpio_local_tgl_gpio_pin(unsigned int pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].ovrt = 1 << (pin & 0x1F); +} + +/*! \brief Initializes the configuration of a GPIO pin so that it can be used + * with GPIO open-drain functions. + * + * \note This function must have been called at least once before using + * \ref gpio_local_set_gpio_open_drain_pin, + * \ref gpio_local_clr_gpio_open_drain_pin or + * \ref gpio_local_tgl_gpio_open_drain_pin. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void gpio_local_init_gpio_open_drain_pin(unsigned int pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F); +} + +/*! \brief Drives a GPIO pin to 1 using open drain. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must + * have been called beforehand. + * + * \note This function does not enable the GPIO mode of the pin. + * \ref gpio_enable_gpio_pin can be called for this purpose. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void gpio_local_set_gpio_open_drain_pin(unsigned int pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F); +} + +/*! \brief Drives a GPIO pin to 0 using open drain. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must + * have been called beforehand. + * + * \note This function does not enable the GPIO mode of the pin. + * \ref gpio_enable_gpio_pin can be called for this purpose. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void gpio_local_clr_gpio_open_drain_pin(unsigned int pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F); +} + +/*! \brief Toggles a GPIO pin using open drain. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must + * have been called beforehand. + * + * \note This function does not enable the GPIO mode of the pin. + * \ref gpio_enable_gpio_pin can be called for this purpose. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void gpio_local_tgl_gpio_open_drain_pin(unsigned int pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].odert = 1 << (pin & 0x1F); +} + +//! @} +#endif // AVR32_GPIO_LOCAL_ADDRESS + +#if UC3L +//! @{ +/*! \name Peripheral Event System support + * + * The GPIO can be programmed to output peripheral events whenever an interrupt + * condition is detected, such as pin value change, or only when a rising or + * falling edge is detected. + * + */ + +/*! \brief Enables the peripheral event generation of a pin. + * + * \param pin The pin number. + * + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void gpio_enable_pin_periph_event(unsigned int pin) +{ + AVR32_GPIO.port[pin >> 5].oderc = 1 << (pin & 0x1F); // The GPIO output driver is disabled for that pin. + AVR32_GPIO.port[pin >> 5].evers = 1 << (pin & 0x1F); +} + +/*! \brief Disables the peripheral event generation of a pin. + * + * \param pin The pin number. + * + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void gpio_disable_pin_periph_event(unsigned int pin) +{ + AVR32_GPIO.port[pin >> 5].everc = 1 << (pin & 0x1F); +} + +/*! \brief Configure the peripheral event trigger mode of a pin + * + * \param pin The pin number. + * \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or + * \ref GPIO_FALLING_EDGE). + * \param use_igf use the Input Glitch Filter (TRUE) or not (FALSE). + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +extern int gpio_configure_pin_periph_event_mode(unsigned int pin, unsigned int mode, unsigned int use_igf); + +//! @} +#endif + + +#endif // _GPIO_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/INTC/exception.x b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/INTC/exception.x new file mode 100644 index 0000000..ec4109d --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/INTC/exception.x @@ -0,0 +1,239 @@ +/* This file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Exception and interrupt vectors. + * + * This file maps all events supported by an AVR32. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#if !__AVR32_UC__ && !__AVR32_AP__ + #error Implementation of the AVR32 architecture not supported by the INTC driver. +#endif + + +#include <avr32/io.h> + + +//! @{ +//! \verbatim + + + .section .exception, "ax", @progbits + + +// Start of Exception Vector Table. + + // EVBA must be aligned with a power of two strictly greater than the EVBA- + // relative offset of the last vector. + .balign 0x200 + + // Export symbol. + .global _evba + .type _evba, @function +_evba: + + .org 0x000 + // Unrecoverable Exception. +_handle_Unrecoverable_Exception: + rjmp $ + + .org 0x004 + // TLB Multiple Hit. +_handle_TLB_Multiple_Hit: + rjmp $ + + .org 0x008 + // Bus Error Data Fetch. +_handle_Bus_Error_Data_Fetch: + rjmp $ + + .org 0x00C + // Bus Error Instruction Fetch. +_handle_Bus_Error_Instruction_Fetch: + rjmp $ + + .org 0x010 + // NMI. +_handle_NMI: + rjmp $ + + .org 0x014 + // Instruction Address. +_handle_Instruction_Address: + rjmp $ + + .org 0x018 + // ITLB Protection. +_handle_ITLB_Protection: + rjmp $ + + .org 0x01C + // Breakpoint. +_handle_Breakpoint: + rjmp $ + + .org 0x020 + // Illegal Opcode. +_handle_Illegal_Opcode: + rjmp $ + + .org 0x024 + // Unimplemented Instruction. +_handle_Unimplemented_Instruction: + rjmp $ + + .org 0x028 + // Privilege Violation. +_handle_Privilege_Violation: + rjmp $ + + .org 0x02C + // Floating-Point: UNUSED IN AVR32UC and AVR32AP. +_handle_Floating_Point: + rjmp $ + + .org 0x030 + // Coprocessor Absent: UNUSED IN AVR32UC. +_handle_Coprocessor_Absent: + rjmp $ + + .org 0x034 + // Data Address (Read). +_handle_Data_Address_Read: + rjmp $ + + .org 0x038 + // Data Address (Write). +_handle_Data_Address_Write: + rjmp $ + + .org 0x03C + // DTLB Protection (Read). +_handle_DTLB_Protection_Read: + rjmp $ + + .org 0x040 + // DTLB Protection (Write). +_handle_DTLB_Protection_Write: + rjmp $ + + .org 0x044 + // DTLB Modified: UNUSED IN AVR32UC. +_handle_DTLB_Modified: + rjmp $ + + .org 0x050 + // ITLB Miss. +_handle_ITLB_Miss: + rjmp $ + + .org 0x060 + // DTLB Miss (Read). +_handle_DTLB_Miss_Read: + rjmp $ + + .org 0x070 + // DTLB Miss (Write). +_handle_DTLB_Miss_Write: + rjmp $ + + .org 0x100 + // Supervisor Call. +_handle_Supervisor_Call: + rjmp $ + + +// Interrupt support. +// The interrupt controller must provide the offset address relative to EVBA. +// Important note: +// All interrupts call a C function named _get_interrupt_handler. +// This function will read group and interrupt line number to then return in +// R12 a pointer to a user-provided interrupt handler. + + .balign 4 + + .irp priority, 0, 1, 2, 3 +_int\priority: +#if __AVR32_UC__ + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. No other register is saved by hardware. +#elif __AVR32_AP__ + // PC and SR are automatically saved in respectively RAR_INTx and RSR_INTx by + // the CPU upon interrupt entry. No other register is saved by hardware. + pushm r8-r12, lr +#endif + mov r12, \priority // Pass the int_level parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. +#if __AVR32_UC__ + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. +#elif __AVR32_AP__ + breq spint\priority // If this was a spurious interrupt (R12 == NULL), branch. + st.w --sp, r12 // Push the pointer to the interrupt handler onto the system stack since no register may be altered. + popm r8-r12, lr, pc // Restore registers and jump to the handler. +spint\priority: + popm r8-r12, lr +#endif + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + .endr + + +// Constant data area. + + .balign 4 + + // Values to store in the interrupt priority registers for the various interrupt priority levels. + // The interrupt priority registers contain the interrupt priority level and + // the EVBA-relative interrupt vector offset. + .global ipr_val + .type ipr_val, @object +ipr_val: + .word (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int0 - _evba),\ + (AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int1 - _evba),\ + (AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int2 - _evba),\ + (AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int3 - _evba) + + +//! \endverbatim +//! @} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/INTC/intc.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/INTC/intc.c new file mode 100644 index 0000000..84d498d --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/INTC/intc.c @@ -0,0 +1,214 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief INTC driver for AVR32 UC3. + * + * AVR32 Interrupt Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include <avr32/io.h> +#include "compiler.h" +#include "preprocessor.h" +#include "intc.h" + +// define _evba from exception.S +extern void _evba; + +//! Values to store in the interrupt priority registers for the various interrupt priority levels. +extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS]; + +//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space. +//! Each line handler table contains a set of pointers to interrupt handlers. +#if (defined __GNUC__) +#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \ +static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)]; +#elif (defined __ICCAVR32__) +#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \ +static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)]; +#endif +MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~); +#undef DECL_INT_LINE_HANDLER_TABLE + +//! Table containing for each interrupt group the number of interrupt request +//! lines and a pointer to the table of interrupt line handlers. +static const struct +{ + unsigned int num_irqs; + volatile __int_handler *_int_line_handler_table; +} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] = +{ +#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \ + {AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP}, + MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~) +#undef INSERT_INT_LINE_HANDLER_TABLE +}; + + +/*! \brief Default interrupt handler. + * + * \note Taken and adapted from Newlib. + */ +#if (defined __GNUC__) +__attribute__((__interrupt__)) +#elif (defined __ICCAVR32__) +__interrupt +#endif +static void _unhandled_interrupt(void) +{ + // Catch unregistered interrupts. + while (TRUE); +} + + +/*! \brief Gets the interrupt handler of the current event at the \a int_level + * interrupt priority level (called from exception.S). + * + * \param int_level Interrupt priority level to handle. + * + * \return Interrupt handler to execute. + * + * \note Taken and adapted from Newlib. + */ +__int_handler _get_interrupt_handler(unsigned int int_level) +{ + // ICR3 is mapped first, ICR0 last. + // Code in exception.S puts int_level in R12 which is used by AVR32-GCC to + // pass a single argument to a function. + unsigned int int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_level]; + unsigned int int_req = AVR32_INTC.irr[int_grp]; + + // As an interrupt may disappear while it is being fetched by the CPU + // (spurious interrupt caused by a delayed response from an MCU peripheral to + // an interrupt flag clear or interrupt disable instruction), check if there + // are remaining interrupt lines to process. + // If a spurious interrupt occurs, the status register (SR) contains an + // execution mode and interrupt level masks corresponding to a level 0 + // interrupt, whatever the interrupt priority level causing the spurious + // event. This behavior has been chosen because a spurious interrupt has not + // to be a priority one and because it may not cause any trouble to other + // interrupts. + // However, these spurious interrupts place the hardware in an unstable state + // and could give problems in other/future versions of the CPU, so the + // software has to be written so that they never occur. The only safe way of + // achieving this is to always clear or disable peripheral interrupts with the + // following sequence: + // 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR. + // 2: Perform the bus access to the peripheral register that clears or + // disables the interrupt. + // 3: Wait until the interrupt has actually been cleared or disabled by the + // peripheral. This is usually performed by reading from a register in the + // same peripheral (it DOES NOT have to be the same register that was + // accessed in step 2, but it MUST be in the same peripheral), what takes + // bus system latencies into account, but peripheral internal latencies + // (generally 0 cycle) also have to be considered. + // 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR. + // Note that steps 1 and 4 are useless inside interrupt handlers as the + // corresponding interrupt level is automatically masked by IxM (unless IxM is + // explicitly cleared by the software). + // + // Get the right IRQ handler. + // + // If several interrupt lines are active in the group, the interrupt line with + // the highest number is selected. This is to be coherent with the + // prioritization of interrupt groups performed by the hardware interrupt + // controller. + // + // If no handler has been registered for the pending interrupt, + // _unhandled_interrupt will be selected thanks to the initialization of + // _int_line_handler_table_x by INTC_init_interrupts. + // + // exception.S will provide the interrupt handler with a clean interrupt stack + // frame, with nothing more pushed onto the stack. The interrupt handler must + // manage the `rete' instruction, what can be done thanks to pure assembly, + // inline assembly or the `__attribute__((__interrupt__))' C function + // attribute. + return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL; +} + +//! Init EVBA address. This sequence might also be done in the UTILS/STARTUP/GCC/crt0.S +static __inline__ void INTC_init_evba(void) +{ + Set_system_register(AVR32_EVBA, (int)&_evba ); +} + +void INTC_init_interrupts(void) +{ + unsigned int int_grp, int_req; + + INTC_init_evba(); + + // For all interrupt groups, + for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++) + { + // For all interrupt request lines of each group, + for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++) + { + // Assign _unhandled_interrupt as default interrupt handler. + _int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt; + } + + // Set the interrupt group priority register to its default value. + // By default, all interrupt groups are linked to the interrupt priority + // level 0 and to the interrupt vector _int0. + AVR32_INTC.ipr[int_grp] = ipr_val[AVR32_INTC_INT0]; + } +} + + +void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level) +{ + // Determine the group of the IRQ. + unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP; + + // Store in _int_line_handler_table_x the pointer to the interrupt handler, so + // that _get_interrupt_handler can retrieve it when the interrupt is vectored. + _int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler; + + // Program the corresponding IPRX register to set the interrupt priority level + // and the interrupt vector offset that will be fetched by the core interrupt + // system. + // NOTE: The _intx functions are intermediate assembly functions between the + // core interrupt system and the user interrupt handler. + AVR32_INTC.ipr[int_grp] = ipr_val[int_level & (AVR32_INTC_IPR_INTLEVEL_MASK >> AVR32_INTC_IPR_INTLEVEL_OFFSET)]; +} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/INTC/intc.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/INTC/intc.h new file mode 100644 index 0000000..31a4fc1 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/INTC/intc.h @@ -0,0 +1,100 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief INTC driver for AVR32 UC3. + * + * AVR32 Interrupt Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _INTC_H_ +#define _INTC_H_ + +#include "compiler.h" + + +//! Maximal number of interrupt request lines per group. +#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP 32 + +//! Number of interrupt priority levels. +#define AVR32_INTC_NUM_INT_LEVELS (1 << AVR32_INTC_IPR_INTLEVEL_SIZE) + + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +//! Pointer to interrupt handler. +#if (defined __GNUC__) +typedef void (*__int_handler)(void); +#elif (defined __ICCAVR32__) +typedef void (__interrupt *__int_handler)(void); +#endif + + +/*! \brief Initializes the hardware interrupt controller driver. + * + * \note Taken and adapted from Newlib. + */ +extern void INTC_init_interrupts(void); + +/*! \brief Registers an interrupt handler. + * + * \param handler Interrupt handler to register. + * \param irq IRQ of the interrupt handler to register. + * \param int_level Interrupt priority level to assign to the group of this IRQ. + * + * \warning The interrupt handler must manage the `rete' instruction, what can + * be done thanks to pure assembly, inline assembly or the + * `__attribute__((__interrupt__))' C function attribute. + * + * \warning If several interrupt handlers of a same group are registered with + * different priority levels, only the latest priority level set will + * be effective. + * + * \note Taken and adapted from Newlib. + */ +extern void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level); + +#endif // __AVR32_ABI_COMPILER__ + + +#endif // _INTC_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm.c new file mode 100644 index 0000000..76d9268 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm.c @@ -0,0 +1,546 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Power Manager driver. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include "compiler.h" +#include "pm.h" + + +/*! \name PM Writable Bit-Field Registers + */ +//! @{ + +typedef union +{ + unsigned long mcctrl; + avr32_pm_mcctrl_t MCCTRL; +} u_avr32_pm_mcctrl_t; + +typedef union +{ + unsigned long cksel; + avr32_pm_cksel_t CKSEL; +} u_avr32_pm_cksel_t; + +typedef union +{ + unsigned long pll; + avr32_pm_pll_t PLL; +} u_avr32_pm_pll_t; + +typedef union +{ + unsigned long oscctrl0; + avr32_pm_oscctrl0_t OSCCTRL0; +} u_avr32_pm_oscctrl0_t; + +typedef union +{ + unsigned long oscctrl1; + avr32_pm_oscctrl1_t OSCCTRL1; +} u_avr32_pm_oscctrl1_t; + +typedef union +{ + unsigned long oscctrl32; + avr32_pm_oscctrl32_t OSCCTRL32; +} u_avr32_pm_oscctrl32_t; + +typedef union +{ + unsigned long ier; + avr32_pm_ier_t IER; +} u_avr32_pm_ier_t; + +typedef union +{ + unsigned long idr; + avr32_pm_idr_t IDR; +} u_avr32_pm_idr_t; + +typedef union +{ + unsigned long icr; + avr32_pm_icr_t ICR; +} u_avr32_pm_icr_t; + +typedef union +{ + unsigned long gcctrl; + avr32_pm_gcctrl_t GCCTRL; +} u_avr32_pm_gcctrl_t; + +typedef union +{ + unsigned long rccr; + avr32_pm_rccr_t RCCR; +} u_avr32_pm_rccr_t; + +typedef union +{ + unsigned long bgcr; + avr32_pm_bgcr_t BGCR; +} u_avr32_pm_bgcr_t; + +typedef union +{ + unsigned long vregcr; + avr32_pm_vregcr_t VREGCR; +} u_avr32_pm_vregcr_t; + +typedef union +{ + unsigned long bod; + avr32_pm_bod_t BOD; +} u_avr32_pm_bod_t; + +//! @} + + +/*! \brief Sets the mode of the oscillator 0. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + * \param mode Oscillator 0 mode (i.e. AVR32_PM_OSCCTRL0_MODE_x). + */ +static void pm_set_osc0_mode(volatile avr32_pm_t *pm, unsigned int mode) +{ + // Read + u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0}; + // Modify + u_avr32_pm_oscctrl0.OSCCTRL0.mode = mode; + // Write + pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0; +} + + +void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm) +{ + pm_set_osc0_mode(pm, AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK); +} + + +void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0) +{ + pm_set_osc0_mode(pm, (fosc0 < 900000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G0 : + (fosc0 < 3000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G1 : + (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 : + AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3); +} + + +void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup) +{ + pm_enable_clk0_no_wait(pm, startup); + pm_wait_for_clk0_ready(pm); +} + + +void pm_disable_clk0(volatile avr32_pm_t *pm) +{ + pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC0EN_MASK; +} + + +void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup) +{ + // Read register + u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0}; + // Modify + u_avr32_pm_oscctrl0.OSCCTRL0.startup = startup; + // Write back + pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0; + + pm->mcctrl |= AVR32_PM_MCCTRL_OSC0EN_MASK; +} + + +void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_OSC0RDY_MASK)); +} + + +/*! \brief Sets the mode of the oscillator 1. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + * \param mode Oscillator 1 mode (i.e. AVR32_PM_OSCCTRL1_MODE_x). + */ +static void pm_set_osc1_mode(volatile avr32_pm_t *pm, unsigned int mode) +{ + // Read + u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1}; + // Modify + u_avr32_pm_oscctrl1.OSCCTRL1.mode = mode; + // Write + pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1; +} + + +void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm) +{ + pm_set_osc1_mode(pm, AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK); +} + + +void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1) +{ + pm_set_osc1_mode(pm, (fosc1 < 900000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G0 : + (fosc1 < 3000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G1 : + (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 : + AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3); +} + + +void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup) +{ + pm_enable_clk1_no_wait(pm, startup); + pm_wait_for_clk1_ready(pm); +} + + +void pm_disable_clk1(volatile avr32_pm_t *pm) +{ + pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC1EN_MASK; +} + + +void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup) +{ + // Read register + u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1}; + // Modify + u_avr32_pm_oscctrl1.OSCCTRL1.startup = startup; + // Write back + pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1; + + pm->mcctrl |= AVR32_PM_MCCTRL_OSC1EN_MASK; +} + + +void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_OSC1RDY_MASK)); +} + + +/*! \brief Sets the mode of the 32-kHz oscillator. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + * \param mode 32-kHz oscillator mode (i.e. AVR32_PM_OSCCTRL32_MODE_x). + */ +static void pm_set_osc32_mode(volatile avr32_pm_t *pm, unsigned int mode) +{ + // Read + u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32}; + // Modify + u_avr32_pm_oscctrl32.OSCCTRL32.mode = mode; + // Write + pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32; +} + + +void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm) +{ + pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK); +} + + +void pm_enable_osc32_crystal(volatile avr32_pm_t *pm) +{ + pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_CRYSTAL); +} + + +void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup) +{ + pm_enable_clk32_no_wait(pm, startup); + pm_wait_for_clk32_ready(pm); +} + + +void pm_disable_clk32(volatile avr32_pm_t *pm) +{ + pm->oscctrl32 &= ~AVR32_PM_OSCCTRL32_OSC32EN_MASK; +} + + +void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup) +{ + // Read register + u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32}; + // Modify + u_avr32_pm_oscctrl32.OSCCTRL32.osc32en = 1; + u_avr32_pm_oscctrl32.OSCCTRL32.startup = startup; + // Write back + pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32; +} + + +void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_OSC32RDY_MASK)); +} + + +void pm_cksel(volatile avr32_pm_t *pm, + unsigned int pbadiv, + unsigned int pbasel, + unsigned int pbbdiv, + unsigned int pbbsel, + unsigned int hsbdiv, + unsigned int hsbsel) +{ + u_avr32_pm_cksel_t u_avr32_pm_cksel = {0}; + + u_avr32_pm_cksel.CKSEL.cpusel = hsbsel; + u_avr32_pm_cksel.CKSEL.cpudiv = hsbdiv; + u_avr32_pm_cksel.CKSEL.hsbsel = hsbsel; + u_avr32_pm_cksel.CKSEL.hsbdiv = hsbdiv; + u_avr32_pm_cksel.CKSEL.pbasel = pbasel; + u_avr32_pm_cksel.CKSEL.pbadiv = pbadiv; + u_avr32_pm_cksel.CKSEL.pbbsel = pbbsel; + u_avr32_pm_cksel.CKSEL.pbbdiv = pbbdiv; + + pm->cksel = u_avr32_pm_cksel.cksel; + + // Wait for ckrdy bit and then clear it + while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK)); +} + + +void pm_gc_setup(volatile avr32_pm_t *pm, + unsigned int gc, + unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1) + unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1 + unsigned int diven, + unsigned int div) +{ + u_avr32_pm_gcctrl_t u_avr32_pm_gcctrl = {0}; + + u_avr32_pm_gcctrl.GCCTRL.oscsel = pll_osc; + u_avr32_pm_gcctrl.GCCTRL.pllsel = osc_or_pll; + u_avr32_pm_gcctrl.GCCTRL.diven = diven; + u_avr32_pm_gcctrl.GCCTRL.div = div; + + pm->gcctrl[gc] = u_avr32_pm_gcctrl.gcctrl; +} + + +void pm_gc_enable(volatile avr32_pm_t *pm, + unsigned int gc) +{ + pm->gcctrl[gc] |= AVR32_PM_GCCTRL_CEN_MASK; +} + + +void pm_gc_disable(volatile avr32_pm_t *pm, + unsigned int gc) +{ + pm->gcctrl[gc] &= ~AVR32_PM_GCCTRL_CEN_MASK; +} + + +void pm_pll_setup(volatile avr32_pm_t *pm, + unsigned int pll, + unsigned int mul, + unsigned int div, + unsigned int osc, + unsigned int lockcount) +{ + u_avr32_pm_pll_t u_avr32_pm_pll = {0}; + + u_avr32_pm_pll.PLL.pllosc = osc; + u_avr32_pm_pll.PLL.plldiv = div; + u_avr32_pm_pll.PLL.pllmul = mul; + u_avr32_pm_pll.PLL.pllcount = lockcount; + + pm->pll[pll] = u_avr32_pm_pll.pll; +} + + +void pm_pll_set_option(volatile avr32_pm_t *pm, + unsigned int pll, + unsigned int pll_freq, + unsigned int pll_div2, + unsigned int pll_wbwdisable) +{ + u_avr32_pm_pll_t u_avr32_pm_pll = {pm->pll[pll]}; + u_avr32_pm_pll.PLL.pllopt = pll_freq | (pll_div2 << 1) | (pll_wbwdisable << 2); + pm->pll[pll] = u_avr32_pm_pll.pll; +} + + +unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, + unsigned int pll) +{ + return (pm->pll[pll] & AVR32_PM_PLLOPT_MASK) >> AVR32_PM_PLLOPT_OFFSET; +} + + +void pm_pll_enable(volatile avr32_pm_t *pm, + unsigned int pll) +{ + pm->pll[pll] |= AVR32_PM_PLLEN_MASK; +} + + +void pm_pll_disable(volatile avr32_pm_t *pm, + unsigned int pll) +{ + pm->pll[pll] &= ~AVR32_PM_PLLEN_MASK; +} + + +void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK0_MASK)); +} + + +void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK1_MASK)); +} + + +void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock) +{ + // Read + u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl}; + // Modify + u_avr32_pm_mcctrl.MCCTRL.mcsel = clock; + // Write back + pm->mcctrl = u_avr32_pm_mcctrl.mcctrl; +} + + +void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup) +{ + pm_enable_osc0_crystal(pm, fosc0); // Enable the Osc0 in crystal mode + pm_enable_clk0(pm, startup); // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal + pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0); // Then switch main clock to Osc0 +} + + +void pm_bod_enable_irq(volatile avr32_pm_t *pm) +{ + pm->ier = AVR32_PM_IER_BODDET_MASK; +} + + +void pm_bod_disable_irq(volatile avr32_pm_t *pm) +{ + Bool global_interrupt_enabled = Is_global_interrupt_enabled(); + + if (global_interrupt_enabled) Disable_global_interrupt(); + pm->idr = AVR32_PM_IDR_BODDET_MASK; + pm->isr; + if (global_interrupt_enabled) Enable_global_interrupt(); +} + + +void pm_bod_clear_irq(volatile avr32_pm_t *pm) +{ + pm->icr = AVR32_PM_ICR_BODDET_MASK; +} + + +unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm) +{ + return ((pm->isr & AVR32_PM_ISR_BODDET_MASK) != 0); +} + + +unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm) +{ + return ((pm->imr & AVR32_PM_IMR_BODDET_MASK) != 0); +} + + +unsigned long pm_bod_get_level(volatile avr32_pm_t *pm) +{ + return (pm->bod & AVR32_PM_BOD_LEVEL_MASK) >> AVR32_PM_BOD_LEVEL_OFFSET; +} + + +unsigned long pm_read_gplp(volatile avr32_pm_t *pm, unsigned long gplp) +{ + return pm->gplp[gplp]; +} + + +void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value) +{ + pm->gplp[gplp] = value; +} + + +long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module) +{ + unsigned long domain = module>>5; + unsigned long *regptr = (unsigned long*)(&(pm->cpumask) + domain); + + // Implementation-specific shortcut: the ckMASK registers are contiguous and + // memory-mapped in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK. + + *regptr |= (1<<(module%32)); + + return PASS; +} + +long pm_disable_module(volatile avr32_pm_t *pm, unsigned long module) +{ + unsigned long domain = module>>5; + unsigned long *regptr = (unsigned long*)(&(pm->cpumask) + domain); + + // Implementation-specific shortcut: the ckMASK registers are contiguous and + // memory-mapped in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK. + + *regptr &= ~(1<<(module%32)); + + return PASS; +} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm.h new file mode 100644 index 0000000..ca679f7 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm.h @@ -0,0 +1,493 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Power Manager driver. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _PM_H_ +#define _PM_H_ + +#include <avr32/io.h> +#include "compiler.h" +#include "preprocessor.h" + + +/*! \brief Sets the MCU in the specified sleep mode. + * + * \param mode Sleep mode: + * \arg \c AVR32_PM_SMODE_IDLE: Idle; + * \arg \c AVR32_PM_SMODE_FROZEN: Frozen; + * \arg \c AVR32_PM_SMODE_STANDBY: Standby; + * \arg \c AVR32_PM_SMODE_STOP: Stop; + * \arg \c AVR32_PM_SMODE_DEEP_STOP: DeepStop; + * \arg \c AVR32_PM_SMODE_STATIC: Static. + */ +#define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));} + + +//! Input and output parameters when initializing PM clocks using pm_configure_clocks(). +typedef struct +{ + //! CPU frequency (input/output argument). + unsigned long cpu_f; + + //! PBA frequency (input/output argument). + unsigned long pba_f; + + //! Oscillator 0's external crystal(or external clock) frequency (board dependant) (input argument). + unsigned long osc0_f; + + //! Oscillator 0's external crystal(or external clock) startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument). + unsigned long osc0_startup; +} pm_freq_param_t; + +#define PM_FREQ_STATUS_FAIL (-1) +#define PM_FREQ_STATUS_OK (0) + + +/*! \brief Gets the MCU reset cause. + * + * \param pm Base address of the Power Manager instance (i.e. &AVR32_PM). + * + * \return The MCU reset cause which can be masked with the + * \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm) +{ + return pm->rcause; +} + + +/*! + * \brief This function will enable the external clock mode of the oscillator 0. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the crystal mode of the oscillator 0. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param fosc0 Oscillator 0 crystal frequency (Hz) + */ +extern void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0); + + +/*! + * \brief This function will enable the oscillator 0 to be used with a startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC. + */ +extern void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will disable the oscillator 0. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_disable_clk0(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 0 to be used with no startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 0 startup time, for which the function does not wait. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC. + */ +extern void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will wait until the Osc0 clock is ready. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the external clock mode of the oscillator 1. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the crystal mode of the oscillator 1. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param fosc1 Oscillator 1 crystal frequency (Hz) + */ +extern void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1); + + +/*! + * \brief This function will enable the oscillator 1 to be used with a startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 1 startup time. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC. + */ +extern void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will disable the oscillator 1. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_disable_clk1(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 1 to be used with no startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 1 startup time, for which the function does not wait. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC. + */ +extern void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will wait until the Osc1 clock is ready. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the external clock mode of the 32-kHz oscillator. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the crystal mode of the 32-kHz oscillator. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc32_crystal(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 32 to be used with a startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 32 kHz startup time. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC. + */ +extern void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will disable the oscillator 32. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_disable_clk32(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 32 to be used with no startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 32 kHz startup time, for which the function does not wait. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC. + */ +extern void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will wait until the osc32 clock is ready. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will select all the power manager clocks. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pbadiv Peripheral Bus A clock divisor enable + * \param pbasel Peripheral Bus A select + * \param pbbdiv Peripheral Bus B clock divisor enable + * \param pbbsel Peripheral Bus B select + * \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock) + * \param hsbsel High Speed Bus select (CPU clock = HSB clock ) + */ +extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel); + + +/*! + * \brief This function will setup a generic clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param gc generic clock number (0 for gc0...) + * \param osc_or_pll Use OSC (=0) or PLL (=1) + * \param pll_osc Select Osc0/PLL0 or Osc1/PLL1 + * \param diven Generic clock divisor enable + * \param div Generic clock divisor + */ +extern void pm_gc_setup(volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div); + + +/*! + * \brief This function will enable a generic clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param gc generic clock number (0 for gc0...) + */ +extern void pm_gc_enable(volatile avr32_pm_t *pm, unsigned int gc); + + +/*! + * \brief This function will disable a generic clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param gc generic clock number (0 for gc0...) + */ +extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc); + + +/*! + * \brief This function will setup a PLL. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + * \param mul PLL MUL in the PLL formula + * \param div PLL DIV in the PLL formula + * \param osc OSC number (0 for osc0, 1 for osc1) + * \param lockcount PLL lockount + */ +extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount); + + +/*! + * \brief This function will set a PLL option. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + * \param pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. + * \param pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value) + * \param pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. + */ +extern void pm_pll_set_option(volatile avr32_pm_t *pm, unsigned int pll, unsigned int pll_freq, unsigned int pll_div2, unsigned int pll_wbwdisable); + + +/*! + * \brief This function will get a PLL option. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + * \return Option + */ +extern unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, unsigned int pll); + + +/*! + * \brief This function will enable a PLL. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + */ +extern void pm_pll_enable(volatile avr32_pm_t *pm, unsigned int pll); + + +/*! + * \brief This function will disable a PLL. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + */ +extern void pm_pll_disable(volatile avr32_pm_t *pm, unsigned int pll); + + +/*! + * \brief This function will wait for PLL0 locked + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will wait for PLL1 locked + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will switch the power manager main clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0. + */ +extern void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock); + + +/*! + * \brief Switch main clock to clock Osc0 (crystal mode) + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param fosc0 Oscillator 0 crystal frequency (Hz) + * \param startup Crystal 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC. + */ +extern void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup); + + +/*! \brief Enables the Brown-Out Detector interrupt. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + */ +extern void pm_bod_enable_irq(volatile avr32_pm_t *pm); + + +/*! \brief Disables the Brown-Out Detector interrupt. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + */ +extern void pm_bod_disable_irq(volatile avr32_pm_t *pm); + + +/*! \brief Clears the Brown-Out Detector interrupt flag. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + */ +extern void pm_bod_clear_irq(volatile avr32_pm_t *pm); + + +/*! \brief Gets the Brown-Out Detector interrupt flag. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + * + * \retval 0 No BOD interrupt. + * \retval 1 BOD interrupt pending. + */ +extern unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm); + + +/*! \brief Gets the Brown-Out Detector interrupt enable status. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + * + * \retval 0 BOD interrupt disabled. + * \retval 1 BOD interrupt enabled. + */ +extern unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm); + + +/*! \brief Gets the triggering threshold of the Brown-Out Detector. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + * + * \return Triggering threshold of the BOD. See the electrical characteristics + * in the part datasheet for actual voltage levels. + */ +extern unsigned long pm_bod_get_level(volatile avr32_pm_t *pm); + + +/*! + * \brief Read the content of the PM GPLP registers + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part) + * + * \return The content of the chosen GPLP register. + */ +extern unsigned long pm_read_gplp(volatile avr32_pm_t *pm, unsigned long gplp); + + +/*! + * \brief Write into the PM GPLP registers + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part) + * \param value Value to write + */ +extern void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value); + + +/*! \brief Enable the clock of a module. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param module The module to clock (use one of the defines in the part-specific + * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the + * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks") + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +extern long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module); + +/*! \brief Disable the clock of a module. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param module The module to shut down (use one of the defines in the part-specific + * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the + * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks") + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +extern long pm_disable_module(volatile avr32_pm_t *pm, unsigned long module); + + + +/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks + * according to the user wishes. + * + * This function needs some parameters stored in a pm_freq_param_t structure: + * - cpu_f and pba_f are the wanted frequencies, + * - osc0_f is the oscillator 0 on-board frequency (e.g. FOSC0), + * - osc0_startup is the oscillator 0 startup time (e.g. OSC0_STARTUP). + * + * The function will then configure the clocks using the following rules: + * - It first try to find a valid PLL frequency (the highest possible value to avoid jitter) in order + * to satisfy the CPU frequency, + * - It optimizes the configuration depending the various divide stages, + * - Then, the PBA frequency is configured from the CPU freq. + * - Note that HSB and PBB are configured with the same frequency as CPU. + * - Note also that the number of wait states of the flash read accesses is automatically set-up depending + * the CPU frequency. As a consequence, the application needs the FLASHC driver to compile. + * + * The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f. + * + * \param param pointer on the configuration structure. + * + * \retval PM_FREQ_STATUS_OK Mode successfully initialized. + * \retval PM_FREQ_STATUS_FAIL The configuration can not be done. + */ +extern int pm_configure_clocks(pm_freq_param_t *param); + + +/*! \brief Automatically configure the USB clock. + * + * USB clock is configured to 48MHz, using the PLL1 from the Oscillator0, assuming + * a 12 MHz crystal is connected to it. + */ +extern void pm_configure_usb_clock(void); + + +#endif // _PM_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm_conf_clocks.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm_conf_clocks.c new file mode 100644 index 0000000..8beb83b --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm_conf_clocks.c @@ -0,0 +1,268 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Power Manager clocks configuration helper. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include <string.h> +#include "compiler.h" +#include "pm.h" + +extern void flashc_set_wait_state(unsigned int wait_state); +#if (defined AVR32_FLASHC_210_H_INCLUDED) +extern void flashc_issue_command(unsigned int command, int page_number); +#endif + + +#define PM_MAX_MUL ((1 << AVR32_PM_PLL0_PLLMUL_SIZE) - 1) + + +int pm_configure_clocks(pm_freq_param_t *param) +{ + // Supported frequencies: + // Fosc0 mul div PLL div2_en cpu_f pba_f Comment + // 12 15 1 192 1 12 12 + // 12 9 3 40 1 20 20 PLL out of spec + // 12 15 1 192 1 24 12 + // 12 9 1 120 1 30 15 + // 12 9 3 40 0 40 20 PLL out of spec + // 12 15 1 192 1 48 12 + // 12 15 1 192 1 48 24 + // 12 8 1 108 1 54 27 + // 12 9 1 120 1 60 15 + // 12 9 1 120 1 60 30 + // 12 10 1 132 1 66 16.5 + // + unsigned long in_cpu_f = param->cpu_f; + unsigned long in_osc0_f = param->osc0_f; + unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0; + unsigned long pll_freq, rest; + Bool b_div2_pba, b_div2_cpu; + + // Switch to external Oscillator 0 + pm_switch_to_osc0(&AVR32_PM, in_osc0_f, param->osc0_startup); + + // Start with CPU freq config + if (in_cpu_f == in_osc0_f) + { + param->cpu_f = in_osc0_f; + param->pba_f = in_osc0_f; + return PM_FREQ_STATUS_OK; + } + else if (in_cpu_f < in_osc0_f) + { + // TBD + } + + rest = in_cpu_f % in_osc0_f; + + for (div = 1; div < 32; div++) + { + if ((div * rest) % in_osc0_f == 0) + break; + } + if (div == 32) + return PM_FREQ_STATUS_FAIL; + + mul = (in_cpu_f * div) / in_osc0_f; + + if (mul > PM_MAX_MUL) + return PM_FREQ_STATUS_FAIL; + + // export 2power from PLL div to div2_cpu + while (!(div % 2)) + { + div /= 2; + div2_cpu++; + } + + // Here we know the mul and div parameter of the PLL config. + // . Check out if the PLL has a valid in_cpu_f. + // . Try to have for the PLL frequency (VCO output) the highest possible value + // to reduce jitter. + while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ) + { + if (2 * mul > PM_MAX_MUL) + break; + mul *= 2; + div2_cpu++; + } + + if (div2_cpu != 0) + { + div2_cpu--; + div2_en = 1; + } + + pll_freq = in_osc0_f * mul / (div * (1 << div2_en)); + + // Update real CPU Frequency + param->cpu_f = pll_freq / (1 << div2_cpu); + mul--; + + pm_pll_setup(&AVR32_PM + , 0 // pll + , mul // mul + , div // div + , 0 // osc + , 16 // lockcount + ); + + pm_pll_set_option(&AVR32_PM + , 0 // pll + // PLL clock is lower than 160MHz: need to set pllopt. + , (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0 // pll_freq + , div2_en // pll_div2 + , 0 // pll_wbwdisable + ); + + rest = pll_freq; + while (rest > AVR32_PM_PBA_MAX_FREQ || + rest != param->pba_f) + { + div2_pba++; + rest = pll_freq / (1 << div2_pba); + if (rest < param->pba_f) + break; + } + + // Update real PBA Frequency + param->pba_f = pll_freq / (1 << div2_pba); + + // Enable PLL0 + pm_pll_enable(&AVR32_PM, 0); + + // Wait for PLL0 locked + pm_wait_for_pll0_locked(&AVR32_PM); + + if (div2_cpu) + { + b_div2_cpu = TRUE; + div2_cpu--; + } + else + b_div2_cpu = FALSE; + + if (div2_pba) + { + b_div2_pba = TRUE; + div2_pba--; + } + else + b_div2_pba = FALSE; + + pm_cksel(&AVR32_PM + , b_div2_pba, div2_pba // PBA + , b_div2_cpu, div2_cpu // PBB + , b_div2_cpu, div2_cpu // HSB + ); + + if (param->cpu_f > AVR32_FLASHC_FWS_0_MAX_FREQ) + { + flashc_set_wait_state(1); +#if (defined AVR32_FLASHC_210_H_INCLUDED) + if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ) + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1); + else + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1); +#endif + } + else + { + flashc_set_wait_state(0); +#if (defined AVR32_FLASHC_210_H_INCLUDED) + if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ) + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1); + else + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1); +#endif + } + + pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0); + + return PM_FREQ_STATUS_OK; +} + + +void pm_configure_usb_clock(void) +{ +#if UC3A3 + + // Setup USB GCLK. + pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc + 0, // osc_or_pll: use Osc (if 0) or PLL (if 1) + 0, // pll_osc: select Osc0/PLL0 or Osc1/PLL1 + 0, // diven + 0); // div + + // Enable USB GCLK. + pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB); +#else + // Use 12MHz from OSC0 and generate 96 MHz + pm_pll_setup(&AVR32_PM, 1, // pll. + 7, // mul. + 1, // div. + 0, // osc. + 16); // lockcount. + + pm_pll_set_option(&AVR32_PM, 1, // pll. + 1, // pll_freq: choose the range 80-180MHz. + 1, // pll_div2. + 0); // pll_wbwdisable. + + // start PLL1 and wait forl lock + pm_pll_enable(&AVR32_PM, 1); + + // Wait for PLL1 locked. + pm_wait_for_pll1_locked(&AVR32_PM); + + pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc. + 1, // osc_or_pll: use Osc (if 0) or PLL (if 1). + 1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1. + 0, // diven. + 0); // div. + pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB); +#endif +} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/power_clocks_lib.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/power_clocks_lib.c new file mode 100644 index 0000000..f5fc155 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/power_clocks_lib.c @@ -0,0 +1,566 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief High-level library abstracting features such as oscillators/pll/dfll + * configuration, clock configuration, System-sensible parameters + * configuration, buses clocks configuration, sleep mode, reset. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ +#include "power_clocks_lib.h" + + +//! Device-specific data +#if UC3L +static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param); // FORWARD declaration +#endif + +#if UC3C +static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param); // FORWARD declaration +#endif + +long int pcl_configure_clocks(pcl_freq_param_t *param) +{ +#ifndef AVR32_PM_VERSION_RESETVALUE + // Implementation for UC3A, UC3A3, UC3B parts. + return(pm_configure_clocks(param)); +#else + #ifdef AVR32_PM_410_H_INCLUDED + // Implementation for UC3C parts. + return(pcl_configure_clocks_uc3c(param)); + #else + // Implementation for UC3L parts. + return(pcl_configure_clocks_uc3l(param)); + #endif +#endif +} + + +//! Device-specific implementation +#if UC3L +// FORWARD declaration +static long int pcl_configure_synchronous_clocks( pm_clk_src_t main_clk_src, + unsigned long main_clock_freq_hz, + pcl_freq_param_t *param); + +long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param) +{ + // Supported main clock sources: PCL_MC_RCSYS + + // Supported synchronous clocks frequencies if RCSYS is the main clock source: + // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz. + + // NOTE: by default, this implementation doesn't perform thorough checks on the + // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + +#ifdef AVR32SFW_INPUT_CHECK + // Verify that fCPU >= fPBx + if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f)) + return(-1); +#endif + +#ifdef AVR32SFW_INPUT_CHECK + // Verify that the target frequencies are reachable. + if((param->cpu_f > SCIF_SLOWCLOCK_FREQ_HZ) || (param->pba_f > SCIF_SLOWCLOCK_FREQ_HZ) + || (param->pbb_f > SCIF_SLOWCLOCK_FREQ_HZ)) + return(-1); +#endif + + return(pcl_configure_synchronous_clocks(PM_CLK_SRC_SLOW, SCIF_SLOWCLOCK_FREQ_HZ, param)); +} + + +long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param) +{ + // Supported main clock sources: PCL_MC_RC120M + + // Supported synchronous clocks frequencies if RC120M is the main clock source: + // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz. + + // NOTE: by default, this implementation doesn't perform thorough checks on the + // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + +#ifdef AVR32SFW_INPUT_CHECK + // Verify that fCPU >= fPBx + if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f)) + return(-1); +#endif + +#ifdef AVR32SFW_INPUT_CHECK + // Verify that the target frequencies are reachable. + if((param->cpu_f > SCIF_RC120M_FREQ_HZ) || (param->pba_f > SCIF_RC120M_FREQ_HZ) + || (param->pbb_f > SCIF_RC120M_FREQ_HZ)) + return(-1); +#endif + + // Start the 120MHz internal RCosc (RC120M) clock + scif_start_rc120M(); + + return(pcl_configure_synchronous_clocks(PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, param)); +} + + +long int pcl_configure_clocks_osc0(pcl_freq_param_t *param) +{ + // Supported main clock sources: PCL_MC_OSC0 + + // Supported synchronous clocks frequencies if OSC0 is the main clock source: + // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example) + // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz. + + // NOTE: by default, this implementation doesn't perform thorough checks on the + // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + + unsigned long main_clock_freq; + + +#ifdef AVR32SFW_INPUT_CHECK + // Verify that fCPU >= fPBx + if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f)) + return(-1); +#endif + + main_clock_freq = param->osc0_f; +#ifdef AVR32SFW_INPUT_CHECK + // Verify that the target frequencies are reachable. + if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq) + || (param->pbb_f > main_clock_freq)) + return(-1); +#endif + // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency. + scif_configure_osc_crystalmode(SCIF_OSC0, main_clock_freq); + // Enable the OSC0 + scif_enable_osc(SCIF_OSC0, param->osc0_startup, true); + + return(pcl_configure_synchronous_clocks(PM_CLK_SRC_OSC0, main_clock_freq, param)); +} + + +long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param) +{ + // Supported main clock sources: PCL_MC_DFLL + + // Supported synchronous clocks frequencies if DFLL is the main clock source: + // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example) + // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz. + + // NOTE: by default, this implementation doesn't perform thorough checks on the + // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + + unsigned long main_clock_freq; + scif_gclk_opt_t *pgc_dfllif_ref_opt; + + +#ifdef AVR32SFW_INPUT_CHECK + // Verify that fCPU >= fPBx + if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f)) + return(-1); +#endif + + main_clock_freq = param->dfll_f; +#ifdef AVR32SFW_INPUT_CHECK + // Verify that the target DFLL output frequency is in the correct range. + if((main_clock_freq > SCIF_DFLL_MAXFREQ_HZ) || (main_clock_freq < SCIF_DFLL_MINFREQ_HZ)) + return(-1); + // Verify that the target frequencies are reachable. + if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq) + || (param->pbb_f > main_clock_freq)) + return(-1); +#endif + pgc_dfllif_ref_opt = (scif_gclk_opt_t *)param->pextra_params; + // Implementation note: this implementation configures the DFLL in closed-loop + // mode (because it gives the best accuracy) which enables the generic clock CLK_DFLLIF_REF + // as a reference (RCSYS being used as the generic clock source, undivided). + scif_dfll0_closedloop_configure_and_start(pgc_dfllif_ref_opt, main_clock_freq, TRUE); + + return(pcl_configure_synchronous_clocks(PM_CLK_SRC_DFLL0, main_clock_freq, param)); +} + + +static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param) +{ + // Supported main clock sources: PCL_MC_RCSYS, PCL_MC_OSC0, PCL_MC_DFLL0, PCL_MC_RC120M + + // Supported synchronous clocks frequencies if RCSYS is the main clock source: + // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz. + + // Supported synchronous clocks frequencies if RC120M is the main clock source: + // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz. + + // Supported synchronous clocks frequencies if OSC0 is the main clock source: + // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example) + // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz. + + // Supported synchronous clocks frequencies if DFLL is the main clock source: + // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example) + // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz. + + // NOTE: by default, this implementation doesn't perform thorough checks on the + // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + + +#ifdef AVR32SFW_INPUT_CHECK + // Verify that fCPU >= fPBx + if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f)) + return(-1); +#endif + + if(PCL_MC_RCSYS == param->main_clk_src) + { + return(pcl_configure_clocks_rcsys(param)); + } + else if(PCL_MC_RC120M == param->main_clk_src) + { + return(pcl_configure_clocks_rc120m(param)); + } + else if(PCL_MC_OSC0 == param->main_clk_src) + { + return(pcl_configure_clocks_osc0(param)); + } + else // PCL_MC_DFLL0 == param->main_clk_src + { + return(pcl_configure_clocks_dfll0(param)); + } +} + +static long int pcl_configure_synchronous_clocks(pm_clk_src_t main_clk_src, unsigned long main_clock_freq_hz, pcl_freq_param_t *param) +{ + //# + //# Set the Synchronous clock division ratio for each clock domain + //# + pm_set_all_cksel(main_clock_freq_hz, param->cpu_f, param->pba_f, param->pbb_f); + + //# + //# Set the Flash wait state and the speed read mode (depending on the target CPU frequency). + //# +#if UC3L + flashcdw_set_flash_waitstate_and_readmode(param->cpu_f); +#elif UC3C + flashc_set_flash_waitstate_and_readmode(param->cpu_f); +#endif + + + //# + //# Switch the main clock source to the selected clock. + //# + pm_set_mclk_source(main_clk_src); + + return PASS; +} + +#endif // UC3L device-specific implementation + +//! UC3C Device-specific implementation +#if UC3C +static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param) +{ + #define PM_MAX_MUL ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1) + #define AVR32_PM_PBA_MAX_FREQ 66000000 + #define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ 240000000 + #define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ 160000000 + + // Implementation for UC3C parts. + // Supported frequencies: + // Fosc0 mul div PLL div2_en cpu_f pba_f Comment + // 12 15 1 192 1 12 12 + // 12 9 3 40 1 20 20 PLL out of spec + // 12 15 1 192 1 24 12 + // 12 9 1 120 1 30 15 + // 12 9 3 40 0 40 20 PLL out of spec + // 12 15 1 192 1 48 12 + // 12 15 1 192 1 48 24 + // 12 8 1 108 1 54 27 + // 12 9 1 120 1 60 15 + // 12 9 1 120 1 60 30 + // 12 10 1 132 1 66 16.5 + // + unsigned long in_cpu_f = param->cpu_f; + unsigned long in_osc0_f = param->osc0_f; + unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0; + unsigned long pll_freq, rest; + Bool b_div2_pba, b_div2_cpu; + + // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency. + scif_configure_osc_crystalmode(SCIF_OSC0, in_osc0_f); + // Enable the OSC0 + scif_enable_osc(SCIF_OSC0, param->osc0_startup, true); + // Set the main clock source as being OSC0. + pm_set_mclk_source(PM_CLK_SRC_OSC0); + + // Start with CPU freq config + if (in_cpu_f == in_osc0_f) + { + param->cpu_f = in_osc0_f; + param->pba_f = in_osc0_f; + return PASS; + } + else if (in_cpu_f < in_osc0_f) + { + // TBD + } + + rest = in_cpu_f % in_osc0_f; + + for (div = 1; div < 32; div++) + { + if ((div * rest) % in_osc0_f == 0) + break; + } + if (div == 32) + return FAIL; + + mul = (in_cpu_f * div) / in_osc0_f; + + if (mul > PM_MAX_MUL) + return FAIL; + + // export 2power from PLL div to div2_cpu + while (!(div % 2)) + { + div /= 2; + div2_cpu++; + } + + // Here we know the mul and div parameter of the PLL config. + // . Check out if the PLL has a valid in_cpu_f. + // . Try to have for the PLL frequency (VCO output) the highest possible value + // to reduce jitter. + while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ) + { + if (2 * mul > PM_MAX_MUL) + break; + mul *= 2; + div2_cpu++; + } + + if (div2_cpu != 0) + { + div2_cpu--; + div2_en = 1; + } + + pll_freq = in_osc0_f * mul / (div * (1 << div2_en)); + + // Update real CPU Frequency + param->cpu_f = pll_freq / (1 << div2_cpu); + mul--; + + scif_pll_opt_t opt; + + opt.osc = SCIF_OSC0, // Sel Osc0 or Osc1 + opt.lockcount = 16, // lockcount in main clock for the PLL wait lock + opt.div = div, // DIV=1 in the formula + opt.mul = mul, // MUL=7 in the formula + opt.pll_div2 = div2_en, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value) + opt.pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. + opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. + + + scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock + + /* Enable PLL0 */ + scif_pll_enable(SCIF_PLL0); + + /* Wait for PLL0 locked */ + scif_wait_for_pll_locked(SCIF_PLL0) ; + + rest = pll_freq; + while (rest > AVR32_PM_PBA_MAX_FREQ || + rest != param->pba_f) + { + div2_pba++; + rest = pll_freq / (1 << div2_pba); + if (rest < param->pba_f) + break; + } + + // Update real PBA Frequency + param->pba_f = pll_freq / (1 << div2_pba); + + + if (div2_cpu) + { + b_div2_cpu = TRUE; + div2_cpu--; + } + else + b_div2_cpu = FALSE; + + if (div2_pba) + { + b_div2_pba = TRUE; + div2_pba--; + } + else + b_div2_pba = FALSE; + + if (b_div2_cpu == TRUE ) + { + pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu); // CPU + pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu); // HSB + pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu); // PBB + } + if (b_div2_pba == TRUE ) + { + pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba); // PBA + pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba); // PBC + } + + // Set Flashc Wait State + flashc_set_flash_waitstate_and_readmode(param->cpu_f); + + // Set the main clock source as being PLL0. + pm_set_mclk_source(PM_CLK_SRC_PLL0); + + return PASS; +} +#endif // UC3C device-specific implementation + +long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup) +{ +#ifndef AVR32_PM_VERSION_RESETVALUE +// Implementation for UC3A, UC3A3, UC3B parts. + if(PCL_OSC0 == osc) + { + // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency, + // enable the OSC0, set the main clock source as being OSC0. + pm_switch_to_osc0(&AVR32_PM, fcrystal, startup); + } + else + { + return PCL_NOT_SUPPORTED; + } +#else +// Implementation for UC3C, UC3L parts. + #if AVR32_PM_VERSION_RESETVALUE < 0x400 + return PCL_NOT_SUPPORTED; + #else + if(PCL_OSC0 == osc) + { + // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency. + scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal); + // Enable the OSC0 + scif_enable_osc(SCIF_OSC0, startup, true); + // Set the Flash wait state and the speed read mode (depending on the target CPU frequency). +#if UC3L + flashcdw_set_flash_waitstate_and_readmode(fcrystal); +#elif UC3C + flashc_set_flash_waitstate_and_readmode(fcrystal); +#endif + // Set the main clock source as being OSC0. + pm_set_mclk_source(PM_CLK_SRC_OSC0); + } + else + { + return PCL_NOT_SUPPORTED; + } + #endif +#endif + return PASS; +} + +long int pcl_configure_usb_clock(void) +{ +#ifndef AVR32_PM_VERSION_RESETVALUE +// Implementation for UC3A, UC3A3, UC3B parts. + pm_configure_usb_clock(); + return PASS; +#else + #ifdef AVR32_PM_410_H_INCLUDED + const scif_pll_opt_t opt = { + .osc = SCIF_OSC0, // Sel Osc0 or Osc1 + .lockcount = 16, // lockcount in main clock for the PLL wait lock + .div = 1, // DIV=1 in the formula + .mul = 5, // MUL=7 in the formula + .pll_div2 = 1, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value) + .pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. + .pll_freq = 1, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. + }; + + /* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */ + scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock + + /* Enable PLL1 */ + scif_pll_enable(SCIF_PLL1); + + /* Wait for PLL1 locked */ + scif_wait_for_pll_locked(SCIF_PLL1) ; + + // Implementation for UC3C parts. + // Setup the generic clock for USB + scif_gc_setup(AVR32_SCIF_GCLK_USB, + SCIF_GCCTRL_PLL1, + AVR32_SCIF_GC_NO_DIV_CLOCK, + 0); + // Now enable the generic clock + scif_gc_enable(AVR32_SCIF_GCLK_USB); + return PASS; + #else + return PCL_NOT_SUPPORTED; + #endif +#endif +} + + +#if UC3L +#else +void pcl_write_gplp(unsigned long gplp, unsigned long value) +{ +#ifndef AVR32_PM_VERSION_RESETVALUE +// Implementation for UC3A, UC3A3, UC3B parts. + pm_write_gplp(&AVR32_PM,gplp,value); +#else + scif_write_gplp(gplp,value); +#endif +} + +unsigned long pcl_read_gplp(unsigned long gplp) +{ +#ifndef AVR32_PM_VERSION_RESETVALUE +// Implementation for UC3A, UC3A3, UC3B parts. + return pm_read_gplp(&AVR32_PM,gplp); +#else + return scif_read_gplp(gplp); +#endif +} +#endif diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/power_clocks_lib.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/power_clocks_lib.h new file mode 100644 index 0000000..28c5888 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/power_clocks_lib.h @@ -0,0 +1,379 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief High-level library abstracting features such as oscillators/pll/dfll + * configuration, clock configuration, System-sensible parameters + * configuration, buses clocks configuration, sleep mode, reset. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _POWER_CLOCKS_LIB_H_ +#define _POWER_CLOCKS_LIB_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <avr32/io.h> +#include "compiler.h" + +#ifndef AVR32_PM_VERSION_RESETVALUE +// Support for UC3A, UC3A3, UC3B parts. + #include "pm.h" +#else +//! Device-specific data +#if UC3L + #include "pm_uc3l.h" + #include "scif_uc3l.h" + #include "flashcdw.h" +#elif UC3C + #include "pm_uc3c.h" + #include "scif_uc3c.h" + #include "flashc.h" +#endif +#endif + +/*! \name Clocks Management + */ +//! @{ + +//! The different oscillators +typedef enum +{ + PCL_OSC0 = 0, + PCL_OSC1 = 1 +} pcl_osc_t; + +//! The different DFLLs +typedef enum +{ + PCL_DFLL0 = 0, + PCL_DFLL1 = 1 +} pcl_dfll_t; + +//! Possible Main Clock Sources +typedef enum +{ + PCL_MC_RCSYS, // Default main clock source, supported by all (aka Slow Clock) + PCL_MC_OSC0, // Supported by all + PCL_MC_OSC1, // Supported by UC3C only + PCL_MC_OSC0_PLL0, // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC0 as reference) + PCL_MC_OSC1_PLL0, // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC1 as reference) + PCL_MC_OSC0_PLL1, // Supported by UC3C (the main clock source is PLL1 with OSC0 as reference) + PCL_MC_OSC1_PLL1, // Supported by UC3C (the main clock source is PLL1 with OSC1 as reference) + PCL_MC_DFLL0, // Supported by UC3L + PCL_MC_DFLL1, // Not supported yet + PCL_MC_RC120M, // Supported by UC3L, UC3C + PCL_MC_RC8M, // Supported by UC3C + PCL_MC_CRIPOSC // Supported by UC3C +} pcl_mainclk_t; + +//! Input and output parameters to configure clocks with pcl_configure_clocks(). +// NOTE: regarding the frequency settings, always abide by the datasheet rules and min & max supported frequencies. +#ifndef AVR32_PM_VERSION_RESETVALUE +// Support for UC3A, UC3A3, UC3B parts. +#define pcl_freq_param_t pm_freq_param_t // See pm.h +#else +// Support for UC3C, UC3L parts. +typedef struct +{ + //! Main clock source selection (input argument). + pcl_mainclk_t main_clk_src; + + //! Target CPU frequency (input/output argument). + unsigned long cpu_f; + + //! Target PBA frequency (input/output argument). + unsigned long pba_f; + + //! Target PBB frequency (input/output argument). + unsigned long pbb_f; + + //! Target PBC frequency (input/output argument). + unsigned long pbc_f; + + //! Oscillator 0's external crystal(or external clock) frequency (board dependant) (input argument). + unsigned long osc0_f; + + //! Oscillator 0's external crystal(or external clock) startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument). + unsigned long osc0_startup; + + //! DFLL target frequency (input/output argument) (NOTE: the bigger, the most stable the frequency) + unsigned long dfll_f; + + //! Other parameters that might be necessary depending on the device (implementation-dependent). + // For the UC3L DFLL setup, this parameter should be pointing to a structure of + // type (scif_gclk_opt_t *). + void *pextra_params; +} pcl_freq_param_t; +#endif + +//! Define "not supported" for the lib. +#define PCL_NOT_SUPPORTED (-10000) + +/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks + * + * This function needs some parameters stored in a pcl_freq_param_t structure: + * - main_clk_src is the id of the main clock source to use, + * - cpu_f and pba_f and pbb_f are the wanted frequencies, + * - osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0), + * - osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP). + * - dfll_f is the target DFLL frequency to set-up if main_clk_src is the dfll. + * + * The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f. + * + * \note: since it is dynamically computing the appropriate field values of the + * configuration registers from the parameters structure, this function is not + * optimal in terms of code size. For a code size optimal solution, it is better + * to create a new function from pcl_configure_clocks() and modify it to use + * preprocessor computation from pre-defined target frequencies. + * + * \param param pointer on the configuration structure. + * + * \retval 0 Success. + * \retval <0 The configuration cannot be performed. + */ +extern long int pcl_configure_clocks(pcl_freq_param_t *param); + +/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the RCSYS osc as main source clock. + * + * This function needs some parameters stored in a pcl_freq_param_t structure: + * - cpu_f and pba_f and pbb_f are the wanted frequencies + * + * Supported main clock sources: PCL_MC_RCSYS + * + * Supported synchronous clocks frequencies: + * 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz. + * + * \note: by default, this implementation doesn't perform thorough checks on the + * input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + * + * \note: since it is dynamically computing the appropriate field values of the + * configuration registers from the parameters structure, this function is not + * optimal in terms of code size. For a code size optimal solution, it is better + * to create a new function from pcl_configure_clocks_rcsys() and modify it to use + * preprocessor computation from pre-defined target frequencies. + * + * \param param pointer on the configuration structure. + * + * \retval 0 Success. + * \retval <0 The configuration cannot be performed. + */ +extern long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param); + +/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the RC120M osc as main source clock. + * + * This function needs some parameters stored in a pcl_freq_param_t structure: + * - cpu_f and pba_f and pbb_f are the wanted frequencies + * + * Supported main clock sources: PCL_MC_RC120M + * + * Supported synchronous clocks frequencies: + * 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz. + * + * \note: by default, this implementation doesn't perform thorough checks on the + * input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + * + * \note: since it is dynamically computing the appropriate field values of the + * configuration registers from the parameters structure, this function is not + * optimal in terms of code size. For a code size optimal solution, it is better + * to create a new function from pcl_configure_clocks_rc120m() and modify it to + * use preprocessor computation from pre-defined target frequencies. + * + * \param param pointer on the configuration structure. + * + * \retval 0 Success. + * \retval <0 The configuration cannot be performed. + */ +extern long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param); + +/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the OSC0 osc as main source clock + * + * This function needs some parameters stored in a pcl_freq_param_t structure: + * - cpu_f and pba_f and pbb_f are the wanted frequencies, + * - osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0), + * - osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP). + * + * Supported main clock sources: PCL_MC_OSC0 + * + * Supported synchronous clocks frequencies: + * (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example) + * 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz. + * + * \note: by default, this implementation doesn't perform thorough checks on the + * input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + * + * \note: since it is dynamically computing the appropriate field values of the + * configuration registers from the parameters structure, this function is not + * optimal in terms of code size. For a code size optimal solution, it is better + * to create a new function from pcl_configure_clocks_osc0() and modify it to use + * preprocessor computation from pre-defined target frequencies. + * + * \param param pointer on the configuration structure. + * + * \retval 0 Success. + * \retval <0 The configuration cannot be performed. + */ +extern long int pcl_configure_clocks_osc0(pcl_freq_param_t *param); + +/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the DFLL0 as main source clock + * + * This function needs some parameters stored in a pcl_freq_param_t structure: + * - cpu_f and pba_f and pbb_f are the wanted frequencies, + * - dfll_f is the target DFLL frequency to set-up + * + * \note: when the DFLL0 is to be used as main source clock for the synchronous clocks, + * the target frequency of the DFLL should be chosen to be as high as possible + * within the specification range (for stability reasons); the target cpu and pbx + * frequencies will then be reached by appropriate division ratio. + * + * Supported main clock sources: PCL_MC_DFLL0 + * + * Supported synchronous clocks frequencies: + * (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example) + * 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz. + * + * \note: by default, this implementation doesn't perform thorough checks on the + * input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + * + * \note: since it is dynamically computing the appropriate field values of the + * configuration registers from the parameters structure, this function is not + * optimal in terms of code size. For a code size optimal solution, it is better + * to create a new function from pcl_configure_clocks_dfll0() and modify it to + * use preprocessor computation from pre-defined target frequencies. + * + * \param param pointer on the configuration structure. + * + * \retval 0 Success. + * \retval <0 The configuration cannot be performed. + */ +extern long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param); + +/*! \brief Switch the main clock source to Osc0 configured in crystal mode + * + * \param osc The oscillator to enable and switch to. + * \param fcrystal Oscillator external crystal frequency (Hz) + * \param startup Oscillator startup time. + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +extern long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup); + +/*! \brief Enable the clock of a module. + * + * \param module The module to clock (use one of the defines in the part-specific + * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the + * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks" + * or look in the module section). + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +#ifndef AVR32_PM_VERSION_RESETVALUE +// Implementation for UC3A, UC3A3, UC3B parts. +#define pcl_enable_module(module) pm_enable_module(&AVR32_PM, module) +#else +// Implementation for UC3C, UC3L parts. +#define pcl_enable_module(module) pm_enable_module(module) +#endif + +/*! \brief Disable the clock of a module. + * + * \param module The module to shut down (use one of the defines in the part-specific + * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the + * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks" + * or look in the module section). + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +#ifndef AVR32_PM_VERSION_RESETVALUE +// Implementation for UC3A, UC3A3, UC3B parts. +#define pcl_disable_module(module) pm_disable_module(&AVR32_PM, module) +#else +// Implementation for UC3C, UC3L parts. +#define pcl_disable_module(module) pm_disable_module(module) +#endif + +/*! \brief Configure the USB Clock + * + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +extern long int pcl_configure_usb_clock(void); + +//! @} + +/*! \name Power Management + */ +//! @{ +/*! + * \brief Read the content of the GPLP registers + * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part) + * + * \return The content of the chosen GPLP register. + */ +extern unsigned long pcl_read_gplp(unsigned long gplp); + + +/*! + * \brief Write into the GPLP registers + * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part) + * \param value Value to write + */ +extern void pcl_write_gplp(unsigned long gplp, unsigned long value); + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif // _POWER_CLOCKS_LIB_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/SPI/spi.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/SPI/spi.c new file mode 100644 index 0000000..cadb8b1 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/SPI/spi.c @@ -0,0 +1,443 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief SPI driver for AVR32 UC3. + * + * This file defines a useful set of functions for the SPI interface on AVR32 + * devices. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an SPI module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include "spi.h" + +#ifdef FREERTOS_USED + +#include "FreeRTOS.h" +#include "semphr.h" + +#endif + + +/*! \name SPI Writable Bit-Field Registers + */ +//! @{ + +typedef union +{ + unsigned long cr; + avr32_spi_cr_t CR; +} u_avr32_spi_cr_t; + +typedef union +{ + unsigned long mr; + avr32_spi_mr_t MR; +} u_avr32_spi_mr_t; + +typedef union +{ + unsigned long tdr; + avr32_spi_tdr_t TDR; +} u_avr32_spi_tdr_t; + +typedef union +{ + unsigned long ier; + avr32_spi_ier_t IER; +} u_avr32_spi_ier_t; + +typedef union +{ + unsigned long idr; + avr32_spi_idr_t IDR; +} u_avr32_spi_idr_t; + +typedef union +{ + unsigned long csr; + avr32_spi_csr0_t CSR; +} u_avr32_spi_csr_t; + +//! @} + + +#ifdef FREERTOS_USED + +//! The SPI mutex. +static xSemaphoreHandle xSPIMutex; + +#endif + + +/*! \brief Calculates the baudrate divider. + * + * \param options Pointer to a structure containing initialization options for + * an SPI channel. + * \param pba_hz SPI module input clock frequency (PBA clock, Hz). + * + * \return Divider or error code. + * \retval >=0 Success. + * \retval <0 Error. + */ +static int getBaudDiv(const spi_options_t *options, unsigned int pba_hz) +{ + int baudDiv = (pba_hz + options->baudrate / 2) / options->baudrate; + + if (baudDiv <= 0 || baudDiv > 255) { + return -1; + } + + return baudDiv; +} + + +void spi_reset(volatile avr32_spi_t *spi) +{ + spi->cr = AVR32_SPI_CR_SWRST_MASK; +} + + +spi_status_t spi_initSlave(volatile avr32_spi_t *spi, + unsigned char bits, + unsigned char spi_mode) +{ + if (spi_mode > 3 || + bits < 8 || bits > 16) { + return SPI_ERROR_ARGUMENT; + } + + // Reset. + spi->cr = AVR32_SPI_CR_SWRST_MASK; + + // Will use CSR0 offsets; these are the same for CSR0 to CSR3. + spi->csr0 = ((spi_mode >> 1) << AVR32_SPI_CSR0_CPOL_OFFSET) | + (((spi_mode & 0x1) ^ 0x1) << AVR32_SPI_CSR0_NCPHA_OFFSET) | + ((bits - 8) << AVR32_SPI_CSR0_BITS_OFFSET); + + return SPI_OK; +} + + +spi_status_t spi_initTest(volatile avr32_spi_t *spi) +{ + // Reset. + spi->cr = AVR32_SPI_CR_SWRST_MASK; + spi->mr |= AVR32_SPI_MR_MSTR_MASK | // Master Mode. + AVR32_SPI_MR_LLB_MASK; // Local Loopback. + + return SPI_OK; +} + + +spi_status_t spi_initMaster(volatile avr32_spi_t *spi, const spi_options_t *options) +{ + u_avr32_spi_mr_t u_avr32_spi_mr; + + if (options->modfdis > 1) { + return SPI_ERROR_ARGUMENT; + } + + // Reset. + spi->cr = AVR32_SPI_CR_SWRST_MASK; + + // Master Mode. + u_avr32_spi_mr.mr = spi->mr; + u_avr32_spi_mr.MR.mstr = 1; + u_avr32_spi_mr.MR.modfdis = options->modfdis; + u_avr32_spi_mr.MR.llb = 0; + u_avr32_spi_mr.MR.pcs = (1 << AVR32_SPI_MR_PCS_SIZE) - 1; + spi->mr = u_avr32_spi_mr.mr; + + return SPI_OK; +} + + +spi_status_t spi_selectionMode(volatile avr32_spi_t *spi, + unsigned char variable_ps, + unsigned char pcs_decode, + unsigned char delay) +{ + u_avr32_spi_mr_t u_avr32_spi_mr; + + if (variable_ps > 1 || + pcs_decode > 1) { + return SPI_ERROR_ARGUMENT; + } + + u_avr32_spi_mr.mr = spi->mr; + u_avr32_spi_mr.MR.ps = variable_ps; + u_avr32_spi_mr.MR.pcsdec = pcs_decode; + u_avr32_spi_mr.MR.dlybcs = delay; + spi->mr = u_avr32_spi_mr.mr; + + return SPI_OK; +} + + +spi_status_t spi_selectChip(volatile avr32_spi_t *spi, unsigned char chip) +{ +#ifdef FREERTOS_USED + while (pdFALSE == xSemaphoreTake(xSPIMutex, 20)); +#endif + + // Assert all lines; no peripheral is selected. + spi->mr |= AVR32_SPI_MR_PCS_MASK; + + if (spi->mr & AVR32_SPI_MR_PCSDEC_MASK) { + // The signal is decoded; allow up to 15 chips. + if (chip > 14) { + return SPI_ERROR_ARGUMENT; + } + + spi->mr &= ~AVR32_SPI_MR_PCS_MASK | (chip << AVR32_SPI_MR_PCS_OFFSET); + } else { + if (chip > 3) { + return SPI_ERROR_ARGUMENT; + } + + spi->mr &= ~(1 << (AVR32_SPI_MR_PCS_OFFSET + chip)); + } + + return SPI_OK; +} + + +spi_status_t spi_unselectChip(volatile avr32_spi_t *spi, unsigned char chip) +{ + unsigned int timeout = SPI_TIMEOUT; + + while (!(spi->sr & AVR32_SPI_SR_TXEMPTY_MASK)) { + if (!timeout--) { + return SPI_ERROR_TIMEOUT; + } + } + + // Assert all lines; no peripheral is selected. + spi->mr |= AVR32_SPI_MR_PCS_MASK; + + // Last transfer, so deassert the current NPCS if CSAAT is set. + spi->cr = AVR32_SPI_CR_LASTXFER_MASK; + +#ifdef FREERTOS_USED + xSemaphoreGive(xSPIMutex); +#endif + + return SPI_OK; +} + + +spi_status_t spi_setupChipReg(volatile avr32_spi_t *spi, + const spi_options_t *options, + unsigned int pba_hz) +{ + u_avr32_spi_csr_t u_avr32_spi_csr; + + if (options->spi_mode > 3 || + options->stay_act > 1 || + options->bits < 8 || options->bits > 16) { + return SPI_ERROR_ARGUMENT; + } + + int baudDiv = getBaudDiv(options, pba_hz); + + if (baudDiv < 0) { + return SPI_ERROR_ARGUMENT; + } + + // Will use CSR0 offsets; these are the same for CSR0 to CSR3. + u_avr32_spi_csr.csr = 0; + u_avr32_spi_csr.CSR.cpol = options->spi_mode >> 1; + u_avr32_spi_csr.CSR.ncpha = (options->spi_mode & 0x1) ^ 0x1; + u_avr32_spi_csr.CSR.csaat = options->stay_act; + u_avr32_spi_csr.CSR.bits = options->bits - 8; + u_avr32_spi_csr.CSR.scbr = baudDiv; + u_avr32_spi_csr.CSR.dlybs = options->spck_delay; + u_avr32_spi_csr.CSR.dlybct = options->trans_delay; + + switch(options->reg) { + case 0: + spi->csr0 = u_avr32_spi_csr.csr; + break; + case 1: + spi->csr1 = u_avr32_spi_csr.csr; + break; + case 2: + spi->csr2 = u_avr32_spi_csr.csr; + break; + case 3: + spi->csr3 = u_avr32_spi_csr.csr; + break; + default: + return SPI_ERROR_ARGUMENT; + } + +#ifdef FREERTOS_USED + if (!xSPIMutex) + { + // Create the SPI mutex. + vSemaphoreCreateBinary(xSPIMutex); + if (!xSPIMutex) + { + while(1); + } + } +#endif + + return SPI_OK; +} + + +void spi_enable(volatile avr32_spi_t *spi) +{ + spi->cr = AVR32_SPI_CR_SPIEN_MASK; +} + + +void spi_disable(volatile avr32_spi_t *spi) +{ + spi->cr = AVR32_SPI_CR_SPIDIS_MASK; +} + + +int spi_is_enabled(volatile avr32_spi_t *spi) +{ + return (spi->sr & AVR32_SPI_SR_SPIENS_MASK) != 0; +} + + +unsigned char spi_writeRegisterEmptyCheck(volatile avr32_spi_t *spi) +{ + return ((spi->sr & AVR32_SPI_SR_TDRE_MASK) != 0); +} + + +spi_status_t spi_write(volatile avr32_spi_t *spi, unsigned short data) +{ + unsigned int timeout = SPI_TIMEOUT; + + while (!(spi->sr & AVR32_SPI_SR_TDRE_MASK)) { + if (!timeout--) { + return SPI_ERROR_TIMEOUT; + } + } + + spi->tdr = data << AVR32_SPI_TDR_TD_OFFSET; + + return SPI_OK; +} + + +spi_status_t spi_variableSlaveWrite(volatile avr32_spi_t *spi, unsigned short data, + unsigned char pcs, unsigned char lastxfer) +{ + unsigned int timeout = SPI_TIMEOUT; + + if (pcs > 14 || lastxfer > 1) { + return SPI_ERROR_ARGUMENT; + } + + while (!(spi->sr & AVR32_SPI_SR_TDRE_MASK)) { + if (!timeout--) { + return SPI_ERROR_TIMEOUT; + } + } + + spi->tdr = (data << AVR32_SPI_TDR_TD_OFFSET) | + (pcs << AVR32_SPI_TDR_PCS_OFFSET) | + (lastxfer << AVR32_SPI_TDR_LASTXFER_OFFSET); + + return SPI_OK; +} + + +unsigned char spi_writeEndCheck(volatile avr32_spi_t *spi) +{ + return ((spi->sr & AVR32_SPI_SR_TXEMPTY_MASK) != 0); +} + + +unsigned char spi_readRegisterFullCheck(volatile avr32_spi_t *spi) +{ + return ((spi->sr & AVR32_SPI_SR_RDRF_MASK) != 0); +} + + +spi_status_t spi_read(volatile avr32_spi_t *spi, unsigned short *data) +{ + unsigned int timeout = SPI_TIMEOUT; + + while ((spi->sr & (AVR32_SPI_SR_RDRF_MASK | AVR32_SPI_SR_TXEMPTY_MASK)) != + (AVR32_SPI_SR_RDRF_MASK | AVR32_SPI_SR_TXEMPTY_MASK)) { + if (!timeout--) { + return SPI_ERROR_TIMEOUT; + } + } + + *data = spi->rdr >> AVR32_SPI_RDR_RD_OFFSET; + + return SPI_OK; +} + + +unsigned char spi_getStatus(volatile avr32_spi_t *spi) +{ + spi_status_t ret = SPI_OK; + unsigned long sr = spi->sr; + + if (sr & AVR32_SPI_SR_OVRES_MASK) { + ret = SPI_ERROR_OVERRUN; + } + + if (sr & AVR32_SPI_SR_MODF_MASK) { + ret += SPI_ERROR_MODE_FAULT; + } + + if (ret == (SPI_ERROR_OVERRUN + SPI_ERROR_MODE_FAULT)) { + return SPI_ERROR_OVERRUN_AND_MODE_FAULT; + } + else if (ret > 0) { + return ret; + } else { + return SPI_OK; + } +} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/SPI/spi.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/SPI/spi.h new file mode 100644 index 0000000..6dcc928 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/SPI/spi.h @@ -0,0 +1,342 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief SPI driver for AVR32 UC3. + * + * This file defines a useful set of functions for the SPI interface on AVR32 + * devices. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an SPI module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _SPI_H_ +#define _SPI_H_ + +#include <avr32/io.h> + + +//! Time-out value (number of attempts). +#define SPI_TIMEOUT 10000 + + +//! Status codes used by the SPI driver. +typedef enum +{ + SPI_ERROR = -1, + SPI_OK = 0, + SPI_ERROR_TIMEOUT = 1, + SPI_ERROR_ARGUMENT, + SPI_ERROR_OVERRUN, + SPI_ERROR_MODE_FAULT, + SPI_ERROR_OVERRUN_AND_MODE_FAULT +} spi_status_t; + +//! Option structure for SPI channels. +typedef struct +{ + //! The SPI channel to set up. + unsigned char reg; + + //! Preferred baudrate for the SPI. + unsigned int baudrate; + + //! Number of bits in each character (8 to 16). + unsigned char bits; + + //! Delay before first clock pulse after selecting slave (in PBA clock periods). + unsigned char spck_delay; + + //! Delay between each transfer/character (in PBA clock periods). + unsigned char trans_delay; + + //! Sets this chip to stay active after last transfer to it. + unsigned char stay_act; + + //! Which SPI mode to use when transmitting. + unsigned char spi_mode; + + //! Disables the mode fault detection. + //! With this bit cleared, the SPI master mode will disable itself if another + //! master tries to address it. + unsigned char modfdis; +} spi_options_t; + + +/*! \brief Resets the SPI controller. + * + * \param spi Base address of the SPI instance. + */ +extern void spi_reset(volatile avr32_spi_t *spi); + +/*! \brief Initializes the SPI in slave mode. + * + * \param spi Base address of the SPI instance. + * \param bits Number of bits in each transmitted character (8 to 16). + * \param spi_mode Clock polarity and phase. + * + * \return Status. + * \retval SPI_OK Success. + * \retval SPI_ERROR_ARGUMENT Invalid argument(s) passed. + */ +extern spi_status_t spi_initSlave(volatile avr32_spi_t *spi, + unsigned char bits, + unsigned char spi_mode); + +/*! \brief Sets up the SPI in a test mode where the transmitter is connected to + * the receiver (local loopback). + * + * \param spi Base address of the SPI instance. + * + * \return Status. + * \retval SPI_OK Success. + */ +extern spi_status_t spi_initTest(volatile avr32_spi_t *spi); + +/*! \brief Initializes the SPI in master mode. + * + * \param spi Base address of the SPI instance. + * \param options Pointer to a structure containing initialization options. + * + * \return Status. + * \retval SPI_OK Success. + * \retval SPI_ERROR_ARGUMENT Invalid argument(s) passed. + */ +extern spi_status_t spi_initMaster(volatile avr32_spi_t *spi, const spi_options_t *options); + +/*! \brief Sets up how and when the slave chips are selected (master mode only). + * + * \param spi Base address of the SPI instance. + * \param variable_ps Target slave is selected in transfer register for every + * character to transmit. + * \param pcs_decode The four chip select lines are decoded externally. Values + * 0 to 14 can be given to \ref spi_selectChip. + * \param delay Delay in PBA periods between chip selects. + * + * \return Status. + * \retval SPI_OK Success. + * \retval SPI_ERROR_ARGUMENT Invalid argument(s) passed. + */ +extern spi_status_t spi_selectionMode(volatile avr32_spi_t *spi, + unsigned char variable_ps, + unsigned char pcs_decode, + unsigned char delay); + +/*! \brief Selects slave chip. + * + * \param spi Base address of the SPI instance. + * \param chip Slave chip number (normal: 0 to 3, extarnally decoded signal: 0 + * to 14). + * + * \return Status. + * \retval SPI_OK Success. + * \retval SPI_ERROR_ARGUMENT Invalid argument(s) passed. + */ +extern spi_status_t spi_selectChip(volatile avr32_spi_t *spi, unsigned char chip); + +/*! \brief Unselects slave chip. + * + * \param spi Base address of the SPI instance. + * \param chip Slave chip number (normal: 0 to 3, extarnally decoded signal: 0 + * to 14). + * + * \return Status. + * \retval SPI_OK Success. + * \retval SPI_ERROR_TIMEOUT Time-out. + * + * \note Will block program execution until time-out occurs if last transmission + * is not complete. Invoke \ref spi_writeEndCheck beforehand if needed. + */ +extern spi_status_t spi_unselectChip(volatile avr32_spi_t *spi, unsigned char chip); + +/*! \brief Sets options for a specific slave chip. + * + * The baudrate field has to be written before transfer in master mode. Four + * similar registers exist, one for each slave. When using encoded slave + * addressing, reg=0 sets options for slaves 0 to 3, reg=1 for slaves 4 to 7 and + * so on. + * + * \param spi Base address of the SPI instance. + * \param options Pointer to a structure containing initialization options for + * an SPI channel. + * \param pba_hz SPI module input clock frequency (PBA clock, Hz). + * + * \return Status. + * \retval SPI_OK Success. + * \retval SPI_ERROR_ARGUMENT Invalid argument(s) passed. + */ +extern spi_status_t spi_setupChipReg(volatile avr32_spi_t *spi, + const spi_options_t *options, + unsigned int pba_hz); + +/*! \brief Enables the SPI. + * + * \param spi Base address of the SPI instance. + */ +extern void spi_enable(volatile avr32_spi_t *spi); + +/*! \brief Disables the SPI. + * + * Ensures that nothing is transferred while setting up buffers. + * + * \param spi Base address of the SPI instance. + * + * \warning This may cause data loss if used on a slave SPI. + */ +extern void spi_disable(volatile avr32_spi_t *spi); + +/*! \brief Tests if the SPI is enabled. + * + * \param spi Base address of the SPI instance. + * + * \return \c 1 if the SPI is enabled, otherwise \c 0. + */ +extern int spi_is_enabled(volatile avr32_spi_t *spi); + +/*! \brief Checks if there is no data in the transmit register. + * + * \param spi Base address of the SPI instance. + * + * \return Status. + * \retval 1 No data in TDR. + * \retval 0 Some data in TDR. + */ +extern unsigned char spi_writeRegisterEmptyCheck(volatile avr32_spi_t *spi); + +/*! \brief Writes one data word in master fixed peripheral select mode or in + * slave mode. + * + * \param spi Base address of the SPI instance. + * \param data The data word to write. + * + * \return Status. + * \retval SPI_OK Success. + * \retval SPI_ERROR_TIMEOUT Time-out. + * + * \note Will block program execution until time-out occurs if transmitter is + * busy and transmit buffer is full. Invoke + * \ref spi_writeRegisterEmptyCheck beforehand if needed. + * + * \note Once the data has been written to the transmit buffer, the end of + * transmission is not waited for. Invoke \ref spi_writeEndCheck if + * needed. + */ +extern spi_status_t spi_write(volatile avr32_spi_t *spi, unsigned short data); + +/*! \brief Selects a slave in master variable peripheral select mode and writes + * one data word to it. + * + * \param spi Base address of the SPI instance. + * \param data The data word to write. + * \param pcs Slave selector (bit 0 -> nCS line 0, bit 1 -> nCS line 1, + * etc.). + * \param lastxfer Boolean indicating whether this is the last data word + * transfer. + * + * \return Status. + * \retval SPI_OK Success. + * \retval SPI_ERROR_TIMEOUT Time-out. + * \retval SPI_ERROR_ARGUMENT Invalid argument(s) passed. + * + * \note Will block program execution until time-out occurs if transmitter is + * busy and transmit buffer is full. Invoke + * \ref spi_writeRegisterEmptyCheck beforehand if needed. + * + * \note Once the data has been written to the transmit buffer, the end of + * transmission is not waited for. Invoke \ref spi_writeEndCheck if + * needed. + */ +extern spi_status_t spi_variableSlaveWrite(volatile avr32_spi_t *spi, + unsigned short data, + unsigned char pcs, + unsigned char lastxfer); + +/*! \brief Checks if all transmissions are complete. + * + * \param spi Base address of the SPI instance. + * + * \return Status. + * \retval 1 All transmissions complete. + * \retval 0 Transmissions not complete. + */ +extern unsigned char spi_writeEndCheck(volatile avr32_spi_t *spi); + +/*! \brief Checks if there is data in the receive register. + * + * \param spi Base address of the SPI instance. + * + * \return Status. + * \retval 1 Some data in RDR. + * \retval 0 No data in RDR. + */ +extern unsigned char spi_readRegisterFullCheck(volatile avr32_spi_t *spi); + +/*! \brief Reads one data word in master mode or in slave mode. + * + * \param spi Base address of the SPI instance. + * \param data Pointer to the location where to store the received data word. + * + * \return Status. + * \retval SPI_OK Success. + * \retval SPI_ERROR_TIMEOUT Time-out. + * + * \note Will block program execution until time-out occurs if no data is + * received or last transmission is not complete. Invoke + * \ref spi_writeEndCheck or \ref spi_readRegisterFullCheck beforehand if + * needed. + */ +extern spi_status_t spi_read(volatile avr32_spi_t *spi, unsigned short *data); + +/*! \brief Gets status information from the SPI. + * + * \param spi Base address of the SPI instance. + * + * \return Status. + * \retval SPI_OK Success. + * \retval SPI_ERROR_OVERRUN Overrun error. + * \retval SPI_ERROR_MODE_FAULT Mode fault (SPI addressed as slave + * while in master mode). + * \retval SPI_ERROR_OVERRUN_AND_MODE_FAULT Overrun error and mode fault. + */ +extern unsigned char spi_getStatus(volatile avr32_spi_t *spi); + + +#endif // _SPI_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/USART/usart.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/USART/usart.c new file mode 100644 index 0000000..b95882a --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/USART/usart.c @@ -0,0 +1,914 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief USART driver for AVR32 UC3. + * + * This file contains basic functions for the AVR32 USART, with support for all + * modes, settings and clock speeds. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include "compiler.h" +#include "usart.h" + + +//------------------------------------------------------------------------------ +/*! \name Private Functions + */ +//! @{ + + +/*! \brief Checks if the USART is in multidrop mode. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if the USART is in multidrop mode, otherwise \c 0. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +static __inline__ int usart_mode_is_multidrop(volatile avr32_usart_t *usart) +{ + return ((usart->mr >> AVR32_USART_MR_PAR_OFFSET) & AVR32_USART_MR_PAR_MULTI) == AVR32_USART_MR_PAR_MULTI; +} + + +/*! \brief Calculates a clock divider (\e CD) and a fractional part (\e FP) for + * the USART asynchronous modes to generate a baud rate as close as + * possible to the baud rate set point. + * + * Baud rate calculation: + * \f$ Baudrate = \frac{SelectedClock}{Over \times (CD + \frac{FP}{8})} \f$, \e Over being 16 or 8. + * The maximal oversampling is selected if it allows to generate a baud rate close to the set point. + * + * \param usart Base address of the USART instance. + * \param baudrate Baud rate set point. + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Baud rate successfully initialized. + * \retval USART_INVALID_INPUT Baud rate set point is out of range for the given input clock frequency. + */ +static int usart_set_async_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, unsigned long pba_hz) +{ + unsigned int over = (pba_hz >= 16 * baudrate) ? 16 : 8; + unsigned int cd_fp = ((1 << AVR32_USART_BRGR_FP_SIZE) * pba_hz + (over * baudrate) / 2) / (over * baudrate); + unsigned int cd = cd_fp >> AVR32_USART_BRGR_FP_SIZE; + unsigned int fp = cd_fp & ((1 << AVR32_USART_BRGR_FP_SIZE) - 1); + + if (cd < 1 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1) + return USART_INVALID_INPUT; + + usart->mr = (usart->mr & ~(AVR32_USART_MR_USCLKS_MASK | + AVR32_USART_MR_SYNC_MASK | + AVR32_USART_MR_OVER_MASK)) | + AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET | + ((over == 16) ? AVR32_USART_MR_OVER_X16 : AVR32_USART_MR_OVER_X8) << AVR32_USART_MR_OVER_OFFSET; + + usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET | + fp << AVR32_USART_BRGR_FP_OFFSET; + + return USART_SUCCESS; +} + + +/*! \brief Calculates a clock divider (\e CD) for the USART synchronous master + * modes to generate a baud rate as close as possible to the baud rate + * set point. + * + * Baud rate calculation: + * \f$ Baudrate = \frac{SelectedClock}{CD} \f$. + * + * \param usart Base address of the USART instance. + * \param baudrate Baud rate set point. + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Baud rate successfully initialized. + * \retval USART_INVALID_INPUT Baud rate set point is out of range for the given input clock frequency. + */ +static int usart_set_sync_master_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, unsigned long pba_hz) +{ + unsigned int cd = (pba_hz + baudrate / 2) / baudrate; + + if (cd < 1 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1) + return USART_INVALID_INPUT; + + usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) | + AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET | + AVR32_USART_MR_SYNC_MASK; + + usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET; + + return USART_SUCCESS; +} + + +/*! \brief Selects the SCK pin as the source of baud rate for the USART + * synchronous slave modes. + * + * \param usart Base address of the USART instance. + * + * \retval USART_SUCCESS Baud rate successfully initialized. + */ +static int usart_set_sync_slave_baudrate(volatile avr32_usart_t *usart) +{ + usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) | + AVR32_USART_MR_USCLKS_SCK << AVR32_USART_MR_USCLKS_OFFSET | + AVR32_USART_MR_SYNC_MASK; + + return USART_SUCCESS; +} + + +/*! \brief Calculates a clock divider (\e CD) for the USART ISO7816 mode to + * generate an ISO7816 clock as close as possible to the clock set point. + * + * ISO7816 clock calculation: + * \f$ Clock = \frac{SelectedClock}{CD} \f$. + * + * \param usart Base address of the USART instance. + * \param clock ISO7816 clock set point. + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS ISO7816 clock successfully initialized. + * \retval USART_INVALID_INPUT ISO7816 clock set point is out of range for the given input clock frequency. + */ +static int usart_set_iso7816_clock(volatile avr32_usart_t *usart, unsigned int clock, unsigned long pba_hz) +{ + unsigned int cd = (pba_hz + clock / 2) / clock; + + if (cd < 1 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1) + return USART_INVALID_INPUT; + + usart->mr = (usart->mr & ~(AVR32_USART_MR_USCLKS_MASK | + AVR32_USART_MR_SYNC_MASK | + AVR32_USART_MR_OVER_MASK)) | + AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET | + AVR32_USART_MR_OVER_X16 << AVR32_USART_MR_OVER_OFFSET; + + usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET; + + return USART_SUCCESS; +} + + +#if defined(AVR32_USART_400_H_INCLUDED) || \ + defined(AVR32_USART_410_H_INCLUDED) || \ + defined(AVR32_USART_420_H_INCLUDED) || \ + defined(AVR32_USART_440_H_INCLUDED) || \ + defined(AVR32_USART_602_H_INCLUDED) + + +/*! \brief Calculates a clock divider (\e CD) for the USART SPI master mode to + * generate a baud rate as close as possible to the baud rate set point. + * + * Baud rate calculation: + * \f$ Baudrate = \frac{SelectedClock}{CD} \f$. + * + * \param usart Base address of the USART instance. + * \param baudrate Baud rate set point. + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Baud rate successfully initialized. + * \retval USART_INVALID_INPUT Baud rate set point is out of range for the given input clock frequency. + */ +static int usart_set_spi_master_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, unsigned long pba_hz) +{ + unsigned int cd = (pba_hz + baudrate / 2) / baudrate; + + if (cd < 4 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1) + return USART_INVALID_INPUT; + + usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) | + AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET; + + usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET; + + return USART_SUCCESS; +} + + +/*! \brief Selects the SCK pin as the source of baud rate for the USART SPI + * slave mode. + * + * \param usart Base address of the USART instance. + * + * \retval USART_SUCCESS Baud rate successfully initialized. + */ +static int usart_set_spi_slave_baudrate(volatile avr32_usart_t *usart) +{ + usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) | + AVR32_USART_MR_USCLKS_SCK << AVR32_USART_MR_USCLKS_OFFSET; + + return USART_SUCCESS; +} + + +#endif // USART rev. >= 4.0.0 + + +//! @} + + +//------------------------------------------------------------------------------ +/*! \name Initialization Functions + */ +//! @{ + + +void usart_reset(volatile avr32_usart_t *usart) +{ + Bool global_interrupt_enabled = Is_global_interrupt_enabled(); + + // Disable all USART interrupts. + // Interrupts needed should be set explicitly on every reset. + if (global_interrupt_enabled) Disable_global_interrupt(); + usart->idr = 0xFFFFFFFF; + usart->csr; + if (global_interrupt_enabled) Enable_global_interrupt(); + + // Reset mode and other registers that could cause unpredictable behavior after reset. + usart->mr = 0; + usart->rtor = 0; + usart->ttgr = 0; + + // Shutdown TX and RX (will be re-enabled when setup has successfully completed), + // reset status bits and turn off DTR and RTS. + usart->cr = AVR32_USART_CR_RSTRX_MASK | + AVR32_USART_CR_RSTTX_MASK | + AVR32_USART_CR_RSTSTA_MASK | + AVR32_USART_CR_RSTIT_MASK | + AVR32_USART_CR_RSTNACK_MASK | +#ifndef AVR32_USART_440_H_INCLUDED +// Note: Modem Signal Management DTR-DSR-DCD-RI are not included in USART rev.440. + AVR32_USART_CR_DTRDIS_MASK | +#endif + AVR32_USART_CR_RTSDIS_MASK; +} + + +int usart_init_rs232(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // Reset the USART and shutdown TX and RX. + usart_reset(usart); + + // Check input values. + if (!opt || // Null pointer. + opt->charlength < 5 || opt->charlength > 9 || + opt->paritytype > 7 || + opt->stopbits > 2 + 255 || + opt->channelmode > 3 || + usart_set_async_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + if (opt->charlength == 9) + { + // Character length set to 9 bits. MODE9 dominates CHRL. + usart->mr |= AVR32_USART_MR_MODE9_MASK; + } + else + { + // CHRL gives the character length (- 5) when MODE9 = 0. + usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET; + } + + usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET | + opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET; + + if (opt->stopbits > USART_2_STOPBITS) + { + // Set two stop bits + usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET; + // and a timeguard period gives the rest. + usart->ttgr = opt->stopbits - USART_2_STOPBITS; + } + else + // Insert 1, 1.5 or 2 stop bits. + usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET; + + // Set normal mode. + usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) | + AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET; + + // Setup complete; enable communication. + // Enable input and output. + usart->cr = AVR32_USART_CR_RXEN_MASK | + AVR32_USART_CR_TXEN_MASK; + + return USART_SUCCESS; +} + + +int usart_init_rs232_tx_only(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // Reset the USART and shutdown TX and RX. + usart_reset(usart); + + // Check input values. + if (!opt || // Null pointer. + opt->charlength < 5 || opt->charlength > 9 || + opt->paritytype > 7 || + opt->stopbits == 1 || opt->stopbits > 2 + 255 || + opt->channelmode > 3 || + usart_set_sync_master_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + if (opt->charlength == 9) + { + // Character length set to 9 bits. MODE9 dominates CHRL. + usart->mr |= AVR32_USART_MR_MODE9_MASK; + } + else + { + // CHRL gives the character length (- 5) when MODE9 = 0. + usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET; + } + + usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET | + opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET; + + if (opt->stopbits > USART_2_STOPBITS) + { + // Set two stop bits + usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET; + // and a timeguard period gives the rest. + usart->ttgr = opt->stopbits - USART_2_STOPBITS; + } + else + // Insert 1 or 2 stop bits. + usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET; + + // Set normal mode. + usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) | + AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET; + + // Setup complete; enable communication. + // Enable only output as input is not possible in synchronous mode without + // transferring clock. + usart->cr = AVR32_USART_CR_TXEN_MASK; + + return USART_SUCCESS; +} + + +int usart_init_hw_handshaking(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // First: Setup standard RS232. + if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Set hardware handshaking mode. + usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) | + AVR32_USART_MR_MODE_HARDWARE << AVR32_USART_MR_MODE_OFFSET; + + return USART_SUCCESS; +} + + +int usart_init_modem(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // First: Setup standard RS232. + if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Set modem mode. + usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) | + AVR32_USART_MR_MODE_MODEM << AVR32_USART_MR_MODE_OFFSET; + + return USART_SUCCESS; +} + + +int usart_init_sync_master(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // Reset the USART and shutdown TX and RX. + usart_reset(usart); + + // Check input values. + if (!opt || // Null pointer. + opt->charlength < 5 || opt->charlength > 9 || + opt->paritytype > 7 || + opt->stopbits == 1 || opt->stopbits > 2 + 255 || + opt->channelmode > 3 || + usart_set_sync_master_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + if (opt->charlength == 9) + { + // Character length set to 9 bits. MODE9 dominates CHRL. + usart->mr |= AVR32_USART_MR_MODE9_MASK; + } + else + { + // CHRL gives the character length (- 5) when MODE9 = 0. + usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET; + } + + usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET | + opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET; + + if (opt->stopbits > USART_2_STOPBITS) + { + // Set two stop bits + usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET; + // and a timeguard period gives the rest. + usart->ttgr = opt->stopbits - USART_2_STOPBITS; + } + else + // Insert 1 or 2 stop bits. + usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET; + + // Set normal mode. + usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) | + AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET | + AVR32_USART_MR_CLKO_MASK; + + // Setup complete; enable communication. + // Enable input and output. + usart->cr = AVR32_USART_CR_RXEN_MASK | + AVR32_USART_CR_TXEN_MASK; + + return USART_SUCCESS; +} + + +int usart_init_sync_slave(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // Reset the USART and shutdown TX and RX. + usart_reset(usart); + + // Check input values. + if (!opt || // Null pointer. + opt->charlength < 5 || opt->charlength > 9 || + opt->paritytype > 7 || + opt->stopbits == 1 || opt->stopbits > 2 + 255 || + opt->channelmode > 3 || + usart_set_sync_slave_baudrate(usart) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + if (opt->charlength == 9) + { + // Character length set to 9 bits. MODE9 dominates CHRL. + usart->mr |= AVR32_USART_MR_MODE9_MASK; + } + else + { + // CHRL gives the character length (- 5) when MODE9 = 0. + usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET; + } + + usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET | + opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET; + + if (opt->stopbits > USART_2_STOPBITS) + { + // Set two stop bits + usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET; + // and a timeguard period gives the rest. + usart->ttgr = opt->stopbits - USART_2_STOPBITS; + } + else + // Insert 1 or 2 stop bits. + usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET; + + // Set normal mode. + usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) | + AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET; + + // Setup complete; enable communication. + // Enable input and output. + usart->cr = AVR32_USART_CR_RXEN_MASK | + AVR32_USART_CR_TXEN_MASK; + + return USART_SUCCESS; +} + + +int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // First: Setup standard RS232. + if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Set RS485 mode. + usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) | + AVR32_USART_MR_MODE_RS485 << AVR32_USART_MR_MODE_OFFSET; + + return USART_SUCCESS; +} + + +int usart_init_IrDA(volatile avr32_usart_t *usart, const usart_options_t *opt, + long pba_hz, unsigned char irda_filter) +{ + // First: Setup standard RS232. + if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Set IrDA filter. + usart->ifr = irda_filter; + + // Set IrDA mode and activate filtering of input. + usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) | + AVR32_USART_MODE_IRDA << AVR32_USART_MR_MODE_OFFSET | + AVR32_USART_MR_FILTER_MASK; + + return USART_SUCCESS; +} + + +int usart_init_iso7816(volatile avr32_usart_t *usart, const usart_iso7816_options_t *opt, int t, long pba_hz) +{ + // Reset the USART and shutdown TX and RX. + usart_reset(usart); + + // Check input values. + if (!opt || // Null pointer. + opt->paritytype > 1) + return USART_INVALID_INPUT; + + if (t == 0) + { + // Set USART mode to ISO7816, T=0. + // The T=0 protocol always uses 2 stop bits. + usart->mr = AVR32_USART_MR_MODE_ISO7816_T0 << AVR32_USART_MR_MODE_OFFSET | + AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET | + opt->bit_order << AVR32_USART_MR_MSBF_OFFSET; // Allow MSBF in T=0. + } + else if (t == 1) + { + // Only LSB first in the T=1 protocol. + // max_iterations field is only used in T=0 mode. + if (opt->bit_order != 0 || + opt->max_iterations != 0) + return USART_INVALID_INPUT; + + // Set USART mode to ISO7816, T=1. + // The T=1 protocol always uses 1 stop bit. + usart->mr = AVR32_USART_MR_MODE_ISO7816_T1 << AVR32_USART_MR_MODE_OFFSET | + AVR32_USART_MR_NBSTOP_1 << AVR32_USART_MR_NBSTOP_OFFSET; + } + else + return USART_INVALID_INPUT; + + if (usart_set_iso7816_clock(usart, opt->iso7816_hz, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Set FIDI register: bit rate = selected clock/FI_DI_ratio/16. + usart->fidi = opt->fidi_ratio; + + // Set ISO7816 spesific options in the MODE register. + usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET | + AVR32_USART_MR_CLKO_MASK | // Enable clock output. + opt->inhibit_nack << AVR32_USART_MR_INACK_OFFSET | + opt->dis_suc_nack << AVR32_USART_MR_DSNACK_OFFSET | + opt->max_iterations << AVR32_USART_MR_MAX_ITERATION_OFFSET; + + // Setup complete; enable the receiver by default. + usart_iso7816_enable_receiver(usart); + + return USART_SUCCESS; +} + + +#if defined(AVR32_USART_400_H_INCLUDED) || \ + defined(AVR32_USART_410_H_INCLUDED) || \ + defined(AVR32_USART_420_H_INCLUDED) || \ + defined(AVR32_USART_440_H_INCLUDED) || \ + defined(AVR32_USART_602_H_INCLUDED) + + +int usart_init_lin_master(volatile avr32_usart_t *usart, unsigned long baudrate, long pba_hz) +{ + // Reset the USART and shutdown TX and RX. + usart_reset(usart); + + // Check input values. + if (usart_set_async_baudrate(usart, baudrate, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + usart->mr |= AVR32_USART_MR_MODE_LIN_MASTER << AVR32_USART_MR_MODE_OFFSET; // LIN master mode. + + // Setup complete; enable communication. + // Enable input and output. + usart->cr = AVR32_USART_CR_RXEN_MASK | + AVR32_USART_CR_TXEN_MASK; + + return USART_SUCCESS; +} + + +int usart_init_lin_slave(volatile avr32_usart_t *usart, unsigned long baudrate, long pba_hz) +{ + // Reset the USART and shutdown TX and RX. + usart_reset(usart); + + // Check input values. + if (usart_set_async_baudrate(usart, baudrate, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + usart->mr |= AVR32_USART_MR_MODE_LIN_SLAVE << AVR32_USART_MR_MODE_OFFSET; // LIN slave mode. + + // Setup complete; enable communication. + // Enable input and output. + usart->cr = AVR32_USART_CR_RXEN_MASK | + AVR32_USART_CR_TXEN_MASK; + + return USART_SUCCESS; +} + + +int usart_init_spi_master(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz) +{ + // Reset the USART and shutdown TX and RX. + usart_reset(usart); + + // Check input values. + if (!opt || // Null pointer. + opt->charlength < 5 || opt->charlength > 9 || + opt->spimode > 3 || + opt->channelmode > 3 || + usart_set_spi_master_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + if (opt->charlength == 9) + { + // Character length set to 9 bits. MODE9 dominates CHRL. + usart->mr |= AVR32_USART_MR_MODE9_MASK; + } + else + { + // CHRL gives the character length (- 5) when MODE9 = 0. + usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET; + } + + usart->mr |= AVR32_USART_MR_MODE_SPI_MASTER << AVR32_USART_MR_MODE_OFFSET | // SPI master mode. + ((opt->spimode & 0x1) ^ 0x1) << AVR32_USART_MR_SYNC_OFFSET | // SPI clock phase. + opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET | // Channel mode. + (opt->spimode >> 1) << AVR32_USART_MR_MSBF_OFFSET | // SPI clock polarity. + AVR32_USART_MR_CLKO_MASK; // Drive SCK pin. + + // Setup complete; enable communication. + // Enable input and output. + usart->cr = AVR32_USART_CR_RXEN_MASK | + AVR32_USART_CR_TXEN_MASK; + + return USART_SUCCESS; +} + + +int usart_init_spi_slave(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz) +{ + // Reset the USART and shutdown TX and RX. + usart_reset(usart); + + // Check input values. + if (!opt || // Null pointer. + opt->charlength < 5 || opt->charlength > 9 || + opt->spimode > 3 || + opt->channelmode > 3 || + usart_set_spi_slave_baudrate(usart) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + if (opt->charlength == 9) + { + // Character length set to 9 bits. MODE9 dominates CHRL. + usart->mr |= AVR32_USART_MR_MODE9_MASK; + } + else + { + // CHRL gives the character length (- 5) when MODE9 = 0. + usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET; + } + + usart->mr |= AVR32_USART_MR_MODE_SPI_SLAVE << AVR32_USART_MR_MODE_OFFSET | // SPI slave mode. + ((opt->spimode & 0x1) ^ 0x1) << AVR32_USART_MR_SYNC_OFFSET | // SPI clock phase. + opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET | // Channel mode. + (opt->spimode >> 1) << AVR32_USART_MR_MSBF_OFFSET; // SPI clock polarity. + + // Setup complete; enable communication. + // Enable input and output. + usart->cr = AVR32_USART_CR_RXEN_MASK | + AVR32_USART_CR_TXEN_MASK; + + return USART_SUCCESS; +} + + +#endif // USART rev. >= 4.0.0 + + +//! @} + + +//------------------------------------------------------------------------------ +#if defined(AVR32_USART_400_H_INCLUDED) || \ + defined(AVR32_USART_410_H_INCLUDED) || \ + defined(AVR32_USART_420_H_INCLUDED) || \ + defined(AVR32_USART_440_H_INCLUDED) || \ + defined(AVR32_USART_602_H_INCLUDED) + + +/*! \name SPI Control Functions + */ +//! @{ + + +int usart_spi_selectChip(volatile avr32_usart_t *usart) +{ + // Force the SPI chip select. + usart->cr = AVR32_USART_CR_RTSEN_MASK; + + return USART_SUCCESS; +} + + +int usart_spi_unselectChip(volatile avr32_usart_t *usart) +{ + int timeout = USART_DEFAULT_TIMEOUT; + + do + { + if (!timeout--) return USART_FAILURE; + } while (!usart_tx_empty(usart)); + + // Release the SPI chip select. + usart->cr = AVR32_USART_CR_RTSDIS_MASK; + + return USART_SUCCESS; +} + + +//! @} + + +#endif // USART rev. >= 4.0.0 + + +//------------------------------------------------------------------------------ +/*! \name Transmit/Receive Functions + */ +//! @{ + + +int usart_send_address(volatile avr32_usart_t *usart, int address) +{ + // Check if USART is in multidrop / RS485 mode. + if (!usart_mode_is_multidrop(usart)) return USART_MODE_FAULT; + + // Prepare to send an address. + usart->cr = AVR32_USART_CR_SENDA_MASK; + + // Write the address to TX. + usart_bw_write_char(usart, address); + + return USART_SUCCESS; +} + + +int usart_write_char(volatile avr32_usart_t *usart, int c) +{ + if (usart_tx_ready(usart)) + { + usart->thr = (c << AVR32_USART_THR_TXCHR_OFFSET) & AVR32_USART_THR_TXCHR_MASK; + return USART_SUCCESS; + } + else + return USART_TX_BUSY; +} + + +int usart_putchar(volatile avr32_usart_t *usart, int c) +{ + int timeout = USART_DEFAULT_TIMEOUT; + + if (c == '\n') + { + do + { + if (!timeout--) return USART_FAILURE; + } while (usart_write_char(usart, '\r') != USART_SUCCESS); + + timeout = USART_DEFAULT_TIMEOUT; + } + + do + { + if (!timeout--) return USART_FAILURE; + } while (usart_write_char(usart, c) != USART_SUCCESS); + + return USART_SUCCESS; +} + + +int usart_read_char(volatile avr32_usart_t *usart, int *c) +{ + // Check for errors: frame, parity and overrun. In RS485 mode, a parity error + // would mean that an address char has been received. + if (usart->csr & (AVR32_USART_CSR_OVRE_MASK | + AVR32_USART_CSR_FRAME_MASK | + AVR32_USART_CSR_PARE_MASK)) + return USART_RX_ERROR; + + // No error; if we really did receive a char, read it and return SUCCESS. + if (usart_test_hit(usart)) + { + *c = (usart->rhr & AVR32_USART_RHR_RXCHR_MASK) >> AVR32_USART_RHR_RXCHR_OFFSET; + return USART_SUCCESS; + } + else + return USART_RX_EMPTY; +} + + +int usart_getchar(volatile avr32_usart_t *usart) +{ + int c, ret; + + while ((ret = usart_read_char(usart, &c)) == USART_RX_EMPTY); + + if (ret == USART_RX_ERROR) + return USART_FAILURE; + + return c; +} + + +void usart_write_line(volatile avr32_usart_t *usart, const char *string) +{ + while (*string != '\0') + usart_putchar(usart, *string++); +} + + +int usart_get_echo_line(volatile avr32_usart_t *usart) +{ + int rx_char; + int retval = USART_SUCCESS; + + while (1) + { + rx_char = usart_getchar(usart); + if (rx_char == USART_FAILURE) + { + usart_write_line(usart, "Error!!!\n"); + retval = USART_FAILURE; + break; + } + if (rx_char == '\x03') + { + retval = USART_FAILURE; + break; + } + usart_putchar(usart, rx_char); + if (rx_char == '\r') + { + usart_putchar(usart, '\n'); + break; + } + } + + return retval; +} + + +//! @} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/USART/usart.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/USART/usart.h new file mode 100644 index 0000000..bc1c100 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/USART/usart.h @@ -0,0 +1,889 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief USART driver for AVR32 UC3. + * + * This file contains basic functions for the AVR32 USART, with support for all + * modes, settings and clock speeds. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _USART_H_ +#define _USART_H_ + +#include <avr32/io.h> +#include "compiler.h" + + +/*! \name Return Values + */ +//! @{ +#define USART_SUCCESS 0 //!< Successful completion. +#define USART_FAILURE -1 //!< Failure because of some unspecified reason. +#define USART_INVALID_INPUT 1 //!< Input value out of range. +#define USART_INVALID_ARGUMENT -1 //!< Argument value out of range. +#define USART_TX_BUSY 2 //!< Transmitter was busy. +#define USART_RX_EMPTY 3 //!< Nothing was received. +#define USART_RX_ERROR 4 //!< Transmission error occurred. +#define USART_MODE_FAULT 5 //!< USART not in the appropriate mode. +//! @} + +//! Default time-out value (number of attempts). +#define USART_DEFAULT_TIMEOUT 10000 + +/*! \name Parity Settings + */ +//! @{ +#define USART_EVEN_PARITY AVR32_USART_MR_PAR_EVEN //!< Use even parity on character transmission. +#define USART_ODD_PARITY AVR32_USART_MR_PAR_ODD //!< Use odd parity on character transmission. +#define USART_SPACE_PARITY AVR32_USART_MR_PAR_SPACE //!< Use a space as parity bit. +#define USART_MARK_PARITY AVR32_USART_MR_PAR_MARK //!< Use a mark as parity bit. +#define USART_NO_PARITY AVR32_USART_MR_PAR_NONE //!< Don't use a parity bit. +#define USART_MULTIDROP_PARITY AVR32_USART_MR_PAR_MULTI //!< Parity bit is used to flag address characters. +//! @} + +/*! \name Stop Bits Settings + */ +//! @{ +#define USART_1_STOPBIT AVR32_USART_MR_NBSTOP_1 //!< Use 1 stop bit. +#define USART_1_5_STOPBITS AVR32_USART_MR_NBSTOP_1_5 //!< Use 1.5 stop bits. +#define USART_2_STOPBITS AVR32_USART_MR_NBSTOP_2 //!< Use 2 stop bits (for more, just give the number of bits). +//! @} + +/*! \name Channel Modes + */ +//! @{ +#define USART_NORMAL_CHMODE AVR32_USART_MR_CHMODE_NORMAL //!< Normal communication. +#define USART_AUTO_ECHO AVR32_USART_MR_CHMODE_ECHO //!< Echo data. +#define USART_LOCAL_LOOPBACK AVR32_USART_MR_CHMODE_LOCAL_LOOP //!< Local loopback. +#define USART_REMOTE_LOOPBACK AVR32_USART_MR_CHMODE_REMOTE_LOOP //!< Remote loopback. +//! @} + +#if defined(AVR32_USART_400_H_INCLUDED) || \ + defined(AVR32_USART_410_H_INCLUDED) || \ + defined(AVR32_USART_420_H_INCLUDED) || \ + defined(AVR32_USART_440_H_INCLUDED) || \ + defined(AVR32_USART_602_H_INCLUDED) + +/*! \name LIN Node Actions + */ +//! @{ +#define USART_LIN_PUBLISH_ACTION AVR32_USART_LINMR_NACT_PUBLISH //!< The USART transmits the response. +#define USART_LIN_SUBSCRIBE_ACTION AVR32_USART_LINMR_NACT_SUBSCRIBE //!< The USART receives the response. +#define USART_LIN_IGNORE_ACTION AVR32_USART_LINMR_NACT_IGNORE //!< The USART does not transmit and does not receive the reponse. +//! @} + +/*! \name LIN Checksum Types + */ +//! @{ +#define USART_LIN_ENHANCED_CHECKSUM 0 //!< LIN 2.0 "enhanced" checksum. +#define USART_LIN_CLASSIC_CHECKSUM 1 //!< LIN 1.3 "classic" checksum. +//! @} + +#endif // USART rev. >= 4.0.0 + + +//! Input parameters when initializing RS232 and similar modes. +typedef struct +{ + //! Set baud rate of the USART (unused in slave modes). + unsigned long baudrate; + + //! Number of bits to transmit as a character (5 to 9). + unsigned char charlength; + + //! How to calculate the parity bit: \ref USART_EVEN_PARITY, \ref USART_ODD_PARITY, + //! \ref USART_SPACE_PARITY, \ref USART_MARK_PARITY, \ref USART_NO_PARITY or + //! \ref USART_MULTIDROP_PARITY. + unsigned char paritytype; + + //! Number of stop bits between two characters: \ref USART_1_STOPBIT, + //! \ref USART_1_5_STOPBITS, \ref USART_2_STOPBITS or any number from 3 to 257 + //! which will result in a time guard period of that length between characters. + //! \note \ref USART_1_5_STOPBITS is supported in asynchronous modes only. + unsigned short stopbits; + + //! Run the channel in testmode: \ref USART_NORMAL_CHMODE, \ref USART_AUTO_ECHO, + //! \ref USART_LOCAL_LOOPBACK or \ref USART_REMOTE_LOOPBACK. + unsigned char channelmode; +} usart_options_t; + +//! Input parameters when initializing ISO7816 mode. +typedef struct +{ + //! Set the frequency of the ISO7816 clock. + unsigned long iso7816_hz; + + //! The number of ISO7816 clock ticks in every bit period (1 to 2047, 0 = disable clock). + //! Bit rate = \ref iso7816_hz / \ref fidi_ratio. + unsigned short fidi_ratio; + + //! How to calculate the parity bit: \ref USART_EVEN_PARITY for normal mode or + //! \ref USART_ODD_PARITY for inverse mode. + unsigned char paritytype; + + //! Inhibit Non Acknowledge:\n + //! - 0: the NACK is generated;\n + //! - 1: the NACK is not generated. + //! + //! \note This bit will be used only in ISO7816 mode, protocol T = 0 receiver. + int inhibit_nack; + + //! Disable successive NACKs. + //! Successive parity errors are counted up to the value in the \ref max_iterations field. + //! These parity errors generate a NACK on the ISO line. As soon as this value is reached, + //! no addititional NACK is sent on the ISO line. The ITERATION flag is asserted. + int dis_suc_nack; + + //! Max number of repetitions (0 to 7). + unsigned char max_iterations; + + //! Bit order in transmitted characters:\n + //! - 0: LSB first;\n + //! - 1: MSB first. + int bit_order; +} usart_iso7816_options_t; + +#if defined(AVR32_USART_400_H_INCLUDED) || \ + defined(AVR32_USART_410_H_INCLUDED) || \ + defined(AVR32_USART_420_H_INCLUDED) || \ + defined(AVR32_USART_440_H_INCLUDED) || \ + defined(AVR32_USART_602_H_INCLUDED) + +//! Input parameters when initializing SPI mode. +typedef struct +{ + //! Set the frequency of the SPI clock (unused in slave mode). + unsigned long baudrate; + + //! Number of bits to transmit as a character (5 to 9). + unsigned char charlength; + + //! Which SPI mode to use. + unsigned char spimode; + + //! Run the channel in testmode: \ref USART_NORMAL_CHMODE, \ref USART_AUTO_ECHO, + //! \ref USART_LOCAL_LOOPBACK or \ref USART_REMOTE_LOOPBACK. + unsigned char channelmode; +} usart_spi_options_t; + +#endif // USART rev. >= 4.0.0 + + +//------------------------------------------------------------------------------ +/*! \name Initialization Functions + */ +//! @{ + +/*! \brief Resets the USART and disables TX and RX. + * + * \param usart Base address of the USART instance. + */ +extern void usart_reset(volatile avr32_usart_t *usart); + +/*! \brief Sets up the USART to use the standard RS232 protocol. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_rs232(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use the standard RS232 protocol in TX-only mode. + * + * Compared to \ref usart_init_rs232, this function allows very high baud rates + * (up to \a pba_hz instead of \a pba_hz / \c 8) at the expense of full duplex. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + * + * \note The \c 1.5 stop bit is not supported in this mode. + */ +extern int usart_init_rs232_tx_only(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use hardware handshaking. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + * + * \note \ref usart_init_rs232 does not need to be invoked before this function. + */ +extern int usart_init_hw_handshaking(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use the modem protocol, activating dedicated inputs/outputs. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_modem(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use a synchronous RS232-like protocol in master mode. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_sync_master(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use a synchronous RS232-like protocol in slave mode. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_sync_slave(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use the RS485 protocol. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use the IrDA protocol. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * \param irda_filter Counter used to distinguish received ones from zeros. + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_IrDA(volatile avr32_usart_t *usart, const usart_options_t *opt, + long pba_hz, unsigned char irda_filter); + +/*! \brief Sets up the USART to use the ISO7816 T=0 or T=1 smartcard protocols. + * + * The receiver is enabled by default. \ref usart_iso7816_enable_receiver and + * \ref usart_iso7816_enable_transmitter can be called to change the half-duplex + * communication direction. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up ISO7816 communication (see \ref usart_iso7816_options_t). + * \param t ISO7816 mode to use (T=0 or T=1). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_iso7816(volatile avr32_usart_t *usart, const usart_iso7816_options_t *opt, int t, long pba_hz); + +#if defined(AVR32_USART_400_H_INCLUDED) || \ + defined(AVR32_USART_410_H_INCLUDED) || \ + defined(AVR32_USART_420_H_INCLUDED) || \ + defined(AVR32_USART_440_H_INCLUDED) || \ + defined(AVR32_USART_602_H_INCLUDED) + +/*! \brief Sets up the USART to use the LIN master mode. + * + * \param usart Base address of the USART instance. + * \param baudrate Baud rate. + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + */ +extern int usart_init_lin_master(volatile avr32_usart_t *usart, unsigned long baudrate, long pba_hz); + +/*! \brief Sets up the USART to use the LIN slave mode. + * + * \param usart Base address of the USART instance. + * \param baudrate Baud rate. + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + */ +extern int usart_init_lin_slave(volatile avr32_usart_t *usart, unsigned long baudrate, long pba_hz); + +/*! \brief Sets up the USART to use the SPI master mode. + * + * \ref usart_spi_selectChip and \ref usart_spi_unselectChip can be called to + * select or unselect the SPI slave chip. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up SPI mode (see \ref usart_spi_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_spi_master(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use the SPI slave mode. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up SPI mode (see \ref usart_spi_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_spi_slave(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz); + +#endif // USART rev. >= 4.0.0 + +//! @} + + +//------------------------------------------------------------------------------ +/*! \name Read and Reset Error Status Bits + */ +//! @{ + +/*! \brief Resets the error status. + * + * This function resets the status bits indicating that a parity error, + * framing error or overrun has occurred. The RXBRK bit, indicating + * a start/end of break condition on the RX line, is also reset. + * + * \param usart Base address of the USART instance. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_reset_status(volatile avr32_usart_t *usart) +{ + usart->cr = AVR32_USART_CR_RSTSTA_MASK; +} + +/*! \brief Checks if a parity error has occurred since last status reset. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if a parity error has been detected, otherwise \c 0. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ int usart_parity_error(volatile avr32_usart_t *usart) +{ + return (usart->csr & AVR32_USART_CSR_PARE_MASK) != 0; +} + +/*! \brief Checks if a framing error has occurred since last status reset. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if a framing error has been detected, otherwise \c 0. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ int usart_framing_error(volatile avr32_usart_t *usart) +{ + return (usart->csr & AVR32_USART_CSR_FRAME_MASK) != 0; +} + +/*! \brief Checks if an overrun error has occurred since last status reset. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if a overrun error has been detected, otherwise \c 0. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ int usart_overrun_error(volatile avr32_usart_t *usart) +{ + return (usart->csr & AVR32_USART_CSR_OVRE_MASK) != 0; +} + +#if defined(AVR32_USART_400_H_INCLUDED) || \ + defined(AVR32_USART_410_H_INCLUDED) || \ + defined(AVR32_USART_420_H_INCLUDED) || \ + defined(AVR32_USART_440_H_INCLUDED) || \ + defined(AVR32_USART_602_H_INCLUDED) + +/*! \brief Get LIN Error Status + * + * \param usart Base address of the USART instance. + * + * \retval The binary value of the error field. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ int usart_lin_get_error(volatile avr32_usart_t *usart) +{ + return (usart->csr & (AVR32_USART_CSR_LINSNRE_MASK | + AVR32_USART_CSR_LINCE_MASK | + AVR32_USART_CSR_LINIPE_MASK | + AVR32_USART_CSR_LINISFE_MASK | + AVR32_USART_CSR_LINBE_MASK)) >> AVR32_USART_CSR_LINBE_OFFSET; +} + +#endif // USART rev. >= 4.0.0 + +//! @} + + +//------------------------------------------------------------------------------ +/*! \name ISO7816 Control Functions + */ +//! @{ + +/*! \brief Enables the ISO7816 receiver. + * + * The ISO7816 transmitter is disabled. + * + * \param usart Base address of the USART instance. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_iso7816_enable_receiver(volatile avr32_usart_t *usart) +{ + usart->cr = AVR32_USART_CR_TXDIS_MASK | AVR32_USART_CR_RXEN_MASK; +} + +/*! \brief Enables the ISO7816 transmitter. + * + * The ISO7816 receiver is disabled. + * + * \param usart Base address of the USART instance. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_iso7816_enable_transmitter(volatile avr32_usart_t *usart) +{ + usart->cr = AVR32_USART_CR_RXDIS_MASK | AVR32_USART_CR_TXEN_MASK; +} + +//! @} + + +//------------------------------------------------------------------------------ +#if defined(AVR32_USART_400_H_INCLUDED) || \ + defined(AVR32_USART_410_H_INCLUDED) || \ + defined(AVR32_USART_420_H_INCLUDED) || \ + defined(AVR32_USART_440_H_INCLUDED) || \ + defined(AVR32_USART_602_H_INCLUDED) + +/*! \name LIN Control Functions + */ +//! @{ + +/*! \brief Sets the node action. + * + * \param usart Base address of the USART instance. + * \param action The node action: \ref USART_LIN_PUBLISH_ACTION, + * \ref USART_LIN_SUBSCRIBE_ACTION or + * \ref USART_LIN_IGNORE_ACTION. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_lin_set_node_action(volatile avr32_usart_t *usart, unsigned char action) +{ + usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_NACT_MASK) | + action << AVR32_USART_LINMR_NACT_OFFSET; +} + +/*! \brief Enables or disables the Identifier parity. + * + * \param usart Base address of the USART instance. + * \param parity Whether to enable the Identifier parity: \c TRUE or \c FALSE. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_lin_enable_parity(volatile avr32_usart_t *usart, unsigned char parity) +{ + usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_PARDIS_MASK) | + !parity << AVR32_USART_LINMR_PARDIS_OFFSET; +} + +/*! \brief Enables or disables the checksum. + * + * \param usart Base address of the USART instance. + * \param parity Whether to enable the checksum: \c TRUE or \c FALSE. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_lin_enable_checksum(volatile avr32_usart_t *usart, unsigned char checksum) +{ + usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_CHKDIS_MASK) | + !checksum << AVR32_USART_LINMR_CHKDIS_OFFSET; +} + +/*! \brief Sets the checksum type. + * + * \param usart Base address of the USART instance. + * \param chktyp The checksum type: \ref USART_LIN_ENHANCED_CHEKSUM or + * \ref USART_LIN_CLASSIC_CHECKSUM. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_lin_set_checksum(volatile avr32_usart_t *usart, unsigned char chktyp) +{ + usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_CHKTYP_MASK) | + chktyp << AVR32_USART_LINMR_CHKTYP_OFFSET; +} + +/*! \brief Gets the response data length. + * + * \param usart Base address of the USART instance. + * + * \return The response data length. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ unsigned char usart_lin_get_data_length(volatile avr32_usart_t *usart) +{ + if (usart->linmr & AVR32_USART_LINMR_DLM_MASK) + { + unsigned char data_length = 1 << ((usart->linir >> (AVR32_USART_LINIR_IDCHR_OFFSET + 4)) & 0x03); + if (data_length == 1) + data_length = 2; + return data_length; + } + else + return ((usart->linmr & AVR32_USART_LINMR_DLC_MASK) >> AVR32_USART_LINMR_DLC_OFFSET) + 1; +} + +/*! \brief Sets the response data length for LIN 1.x. + * + * \param usart Base address of the USART instance. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_lin_set_data_length_lin1x(volatile avr32_usart_t *usart) +{ + usart->linmr |= AVR32_USART_LINMR_DLM_MASK; +} + +/*! \brief Sets the response data length for LIN 2.x. + * + * \param usart Base address of the USART instance. + * \param data_length The response data length. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_lin_set_data_length_lin2x(volatile avr32_usart_t *usart, unsigned char data_length) +{ + usart->linmr = (usart->linmr & ~(AVR32_USART_LINMR_DLC_MASK | + AVR32_USART_LINMR_DLM_MASK)) | + (data_length - 1) << AVR32_USART_LINMR_DLC_OFFSET; +} + +/*! \brief Enables or disables the frame slot mode. + * + * \param usart Base address of the USART instance. + * \param frameslot Whether to enable the frame slot mode: \c TRUE or + * \c FALSE. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_lin_enable_frameslot(volatile avr32_usart_t *usart, unsigned char frameslot) +{ + usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_FSDIS_MASK) | + !frameslot << AVR32_USART_LINMR_FSDIS_OFFSET; +} + +/*! \brief Gets the Identifier character. + * + * \param usart Base address of the USART instance. + * + * \return The Identifier character. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ unsigned char usart_lin_get_id_char(volatile avr32_usart_t *usart) +{ + return (usart->linir & AVR32_USART_LINIR_IDCHR_MASK) >> AVR32_USART_LINIR_IDCHR_OFFSET; +} + +/*! \brief Sets the Identifier character. + * + * \param usart Base address of the USART instance. + * \param id_char The Identifier character. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_lin_set_id_char(volatile avr32_usart_t *usart, unsigned char id_char) +{ + usart->linir = (usart->linir & ~AVR32_USART_LINIR_IDCHR_MASK) | + id_char << AVR32_USART_LINIR_IDCHR_OFFSET; +} + +//! @} + +#endif // USART rev. >= 4.0.0 + + +//------------------------------------------------------------------------------ +#if defined(AVR32_USART_400_H_INCLUDED) || \ + defined(AVR32_USART_410_H_INCLUDED) || \ + defined(AVR32_USART_420_H_INCLUDED) || \ + defined(AVR32_USART_440_H_INCLUDED) || \ + defined(AVR32_USART_602_H_INCLUDED) + +/*! \name SPI Control Functions + */ +//! @{ + +/*! \brief Selects SPI slave chip. + * + * \param usart Base address of the USART instance. + * + * \retval USART_SUCCESS Success. + */ +extern int usart_spi_selectChip(volatile avr32_usart_t *usart); + +/*! \brief Unselects SPI slave chip. + * + * \param usart Base address of the USART instance. + * + * \retval USART_SUCCESS Success. + * \retval USART_FAILURE Time-out. + */ +extern int usart_spi_unselectChip(volatile avr32_usart_t *usart); + +//! @} + +#endif // USART rev. >= 4.0.0 + + +//------------------------------------------------------------------------------ +/*! \name Transmit/Receive Functions + */ +//! @{ + +/*! \brief Addresses a receiver. + * + * While in RS485 mode, receivers only accept data addressed to them. + * A packet/char with the address tag set has to precede any data. + * This function is used to address a receiver. This receiver should read + * all the following data, until an address packet addresses another receiver. + * + * \param usart Base address of the USART instance. + * \param address Address of the target device. + * + * \retval USART_SUCCESS Address successfully sent (if current mode is RS485). + * \retval USART_MODE_FAULT Wrong operating mode. + */ +extern int usart_send_address(volatile avr32_usart_t *usart, int address); + +/*! \brief Tests if the USART is ready to transmit a character. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if the USART Transmit Holding Register is free, otherwise \c 0. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ int usart_tx_ready(volatile avr32_usart_t *usart) +{ + return (usart->csr & AVR32_USART_CSR_TXRDY_MASK) != 0; +} + +/*! \brief Writes the given character to the TX buffer if the transmitter is ready. + * + * \param usart Base address of the USART instance. + * \param c The character (up to 9 bits) to transmit. + * + * \retval USART_SUCCESS The transmitter was ready. + * \retval USART_TX_BUSY The transmitter was busy. + */ +extern int usart_write_char(volatile avr32_usart_t *usart, int c); + +/*! \brief An active wait writing a character to the USART. + * + * \param usart Base address of the USART instance. + * \param c The character (up to 9 bits) to transmit. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_bw_write_char(volatile avr32_usart_t *usart, int c) +{ + while (usart_write_char(usart, c) != USART_SUCCESS); +} + +/*! \brief Sends a character with the USART. + * + * \param usart Base address of the USART instance. + * \param c Character to write. + * + * \retval USART_SUCCESS The character was written. + * \retval USART_FAILURE The function timed out before the USART transmitter became ready to send. + */ +extern int usart_putchar(volatile avr32_usart_t *usart, int c); + +/*! \brief Tests if all requested USART transmissions are over. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if the USART Transmit Shift Register and the USART Transmit + * Holding Register are free, otherwise \c 0. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ int usart_tx_empty(volatile avr32_usart_t *usart) +{ + return (usart->csr & AVR32_USART_CSR_TXEMPTY_MASK) != 0; +} + +/*! \brief Tests if the USART contains a received character. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if the USART Receive Holding Register is full, otherwise \c 0. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ int usart_test_hit(volatile avr32_usart_t *usart) +{ + return (usart->csr & AVR32_USART_CSR_RXRDY_MASK) != 0; +} + +/*! \brief Checks the RX buffer for a received character, and stores it at the + * given memory location. + * + * \param usart Base address of the USART instance. + * \param c Pointer to the where the read character should be stored + * (must be at least short in order to accept 9-bit characters). + * + * \retval USART_SUCCESS The character was read successfully. + * \retval USART_RX_EMPTY The RX buffer was empty. + * \retval USART_RX_ERROR An error was deteceted. + */ +extern int usart_read_char(volatile avr32_usart_t *usart, int *c); + +/*! \brief Waits until a character is received, and returns it. + * + * \param usart Base address of the USART instance. + * + * \return The received character, or \ref USART_FAILURE upon error. + */ +extern int usart_getchar(volatile avr32_usart_t *usart); + +/*! \brief Writes one character string to the USART. + * + * \param usart Base address of the USART instance. + * \param string String to be written. + */ +extern void usart_write_line(volatile avr32_usart_t *usart, const char *string); + +/*! \brief Gets and echoes characters until end of line. + * + * \param usart Base address of the USART instance. + * + * \retval USART_SUCCESS Success. + * \retval USART_FAILURE Low-level error detected or ETX character received. + */ +extern int usart_get_echo_line(volatile avr32_usart_t *usart); + +#if defined(AVR32_USART_400_H_INCLUDED) || \ + defined(AVR32_USART_410_H_INCLUDED) || \ + defined(AVR32_USART_420_H_INCLUDED) || \ + defined(AVR32_USART_440_H_INCLUDED) || \ + defined(AVR32_USART_602_H_INCLUDED) + +/*! \brief Abort LIN transmission. + * + * \param usart Base address of the USART instance. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_lin_abort(volatile avr32_usart_t *usart) +{ + usart->cr = AVR32_USART_LINABT_MASK; +} + +/*! \brief Tests if a LIN transfer has been completed. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if a LIN transfer has been completed, otherwise \c 0. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +extern __inline__ int usart_lin_transfer_completed(volatile avr32_usart_t *usart) +{ + return (usart->csr & AVR32_USART_CSR_LINTC_MASK) != 0; +} + +#endif // USART rev. >= 4.0.0 + +//! @} + + +#endif // _USART_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS/ctrl_access.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS/ctrl_access.c new file mode 100644 index 0000000..09790c2 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS/ctrl_access.c @@ -0,0 +1,571 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Abstraction layer for memory interfaces. + * + * This module contains the interfaces: + * - MEM <-> USB; + * - MEM <-> RAM; + * - MEM <-> MEM. + * + * This module may be configured and expanded to support the following features: + * - write-protected globals; + * - password-protected data; + * - specific features; + * - etc. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +//_____ I N C L U D E S ____________________________________________________ + +#include "compiler.h" +#include "preprocessor.h" +#ifdef FREERTOS_USED +#include "FreeRTOS.h" +#include "semphr.h" +#endif +#include "ctrl_access.h" + + +//_____ D E F I N I T I O N S ______________________________________________ + +#ifdef FREERTOS_USED + +/*! \name LUN Access Protection Macros + */ +//! @{ + +/*! \brief Locks accesses to LUNs. + * + * \return \c TRUE if the access was successfully locked, else \c FALSE. + */ +#define Ctrl_access_lock() ctrl_access_lock() + +/*! \brief Unlocks accesses to LUNs. + */ +#define Ctrl_access_unlock() xSemaphoreGive(ctrl_access_semphr) + +//! @} + +//! Handle to the semaphore protecting accesses to LUNs. +static xSemaphoreHandle ctrl_access_semphr = NULL; + +#else + +/*! \name LUN Access Protection Macros + */ +//! @{ + +/*! \brief Locks accesses to LUNs. + * + * \return \c TRUE if the access was successfully locked, else \c FALSE. + */ +#define Ctrl_access_lock() TRUE + +/*! \brief Unlocks accesses to LUNs. + */ +#define Ctrl_access_unlock() + +//! @} + +#endif // FREERTOS_USED + + +#if MAX_LUN + +/*! \brief Initializes an entry of the LUN descriptor table. + * + * \param lun Logical Unit Number. + * + * \return LUN descriptor table entry initializer. + */ +#if ACCESS_USB == ENABLED && ACCESS_MEM_TO_RAM == ENABLED +#define Lun_desc_entry(lun) \ + {\ + TPASTE3(Lun_, lun, _test_unit_ready),\ + TPASTE3(Lun_, lun, _read_capacity),\ + TPASTE3(Lun_, lun, _wr_protect),\ + TPASTE3(Lun_, lun, _removal),\ + TPASTE3(Lun_, lun, _usb_read_10),\ + TPASTE3(Lun_, lun, _usb_write_10),\ + TPASTE3(Lun_, lun, _mem_2_ram),\ + TPASTE3(Lun_, lun, _ram_2_mem),\ + TPASTE3(LUN_, lun, _NAME)\ + } +#elif ACCESS_USB == ENABLED +#define Lun_desc_entry(lun) \ + {\ + TPASTE3(Lun_, lun, _test_unit_ready),\ + TPASTE3(Lun_, lun, _read_capacity),\ + TPASTE3(Lun_, lun, _wr_protect),\ + TPASTE3(Lun_, lun, _removal),\ + TPASTE3(Lun_, lun, _usb_read_10),\ + TPASTE3(Lun_, lun, _usb_write_10),\ + TPASTE3(LUN_, lun, _NAME)\ + } +#elif ACCESS_MEM_TO_RAM == ENABLED +#define Lun_desc_entry(lun) \ + {\ + TPASTE3(Lun_, lun, _test_unit_ready),\ + TPASTE3(Lun_, lun, _read_capacity),\ + TPASTE3(Lun_, lun, _wr_protect),\ + TPASTE3(Lun_, lun, _removal),\ + TPASTE3(Lun_, lun, _mem_2_ram),\ + TPASTE3(Lun_, lun, _ram_2_mem),\ + TPASTE3(LUN_, lun, _NAME)\ + } +#else +#define Lun_desc_entry(lun) \ + {\ + TPASTE3(Lun_, lun, _test_unit_ready),\ + TPASTE3(Lun_, lun, _read_capacity),\ + TPASTE3(Lun_, lun, _wr_protect),\ + TPASTE3(Lun_, lun, _removal),\ + TPASTE3(LUN_, lun, _NAME)\ + } +#endif + +//! LUN descriptor table. +static const struct +{ + Ctrl_status (*test_unit_ready)(void); + Ctrl_status (*read_capacity)(U32 *); + Bool (*wr_protect)(void); + Bool (*removal)(void); +#if ACCESS_USB == ENABLED + Ctrl_status (*usb_read_10)(U32, U16); + Ctrl_status (*usb_write_10)(U32, U16); +#endif +#if ACCESS_MEM_TO_RAM == ENABLED + Ctrl_status (*mem_2_ram)(U32, void *); + Ctrl_status (*ram_2_mem)(U32, const void *); +#endif + const char *name; +} lun_desc[MAX_LUN] = +{ +#if LUN_0 == ENABLE + Lun_desc_entry(0), +#endif +#if LUN_1 == ENABLE + Lun_desc_entry(1), +#endif +#if LUN_2 == ENABLE + Lun_desc_entry(2), +#endif +#if LUN_3 == ENABLE + Lun_desc_entry(3), +#endif +#if LUN_4 == ENABLE + Lun_desc_entry(4), +#endif +#if LUN_5 == ENABLE + Lun_desc_entry(5), +#endif +#if LUN_6 == ENABLE + Lun_desc_entry(6), +#endif +#if LUN_7 == ENABLE + Lun_desc_entry(7) +#endif +}; + +#endif + + +#if GLOBAL_WR_PROTECT == ENABLED +Bool g_wr_protect; +#endif + + +/*! \name Control Interface + */ +//! @{ + + +#ifdef FREERTOS_USED + +Bool ctrl_access_init(void) +{ + // If the handle to the protecting semaphore is not valid, + if (!ctrl_access_semphr) + { + // try to create the semaphore. + vSemaphoreCreateBinary(ctrl_access_semphr); + + // If the semaphore could not be created, there is no backup solution. + if (!ctrl_access_semphr) return FALSE; + } + + return TRUE; +} + + +/*! \brief Locks accesses to LUNs. + * + * \return \c TRUE if the access was successfully locked, else \c FALSE. + */ +static Bool ctrl_access_lock(void) +{ + // If the semaphore could not be created, there is no backup solution. + if (!ctrl_access_semphr) return FALSE; + + // Wait for the semaphore. + while (!xSemaphoreTake(ctrl_access_semphr, portMAX_DELAY)); + + return TRUE; +} + +#endif // FREERTOS_USED + + +U8 get_nb_lun(void) +{ +#if MEM_USB == ENABLE + U8 nb_lun; + + if (!Ctrl_access_lock()) return MAX_LUN; + + nb_lun = MAX_LUN + host_get_lun(); + + Ctrl_access_unlock(); + + return nb_lun; +#else + return MAX_LUN; +#endif +} + + +U8 get_cur_lun(void) +{ + return LUN_ID_0; +} + + +Ctrl_status mem_test_unit_ready(U8 lun) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].test_unit_ready() : +#endif +#if LUN_USB == ENABLE + Lun_usb_test_unit_ready(lun - LUN_ID_USB); +#else + CTRL_FAIL; +#endif + + Ctrl_access_unlock(); + + return status; +} + + +Ctrl_status mem_read_capacity(U8 lun, U32 *u32_nb_sector) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].read_capacity(u32_nb_sector) : +#endif +#if LUN_USB == ENABLE + Lun_usb_read_capacity(lun - LUN_ID_USB, u32_nb_sector); +#else + CTRL_FAIL; +#endif + + Ctrl_access_unlock(); + + return status; +} + + +U8 mem_sector_size(U8 lun) +{ + U8 sector_size; + + if (!Ctrl_access_lock()) return 0; + + sector_size = +#if MAX_LUN + (lun < MAX_LUN) ? 1 : +#endif +#if LUN_USB == ENABLE + Lun_usb_read_sector_size(lun - LUN_ID_USB); +#else + 0; +#endif + + Ctrl_access_unlock(); + + return sector_size; +} + + +Bool mem_wr_protect(U8 lun) +{ + Bool wr_protect; + + if (!Ctrl_access_lock()) return TRUE; + + wr_protect = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].wr_protect() : +#endif +#if LUN_USB == ENABLE + Lun_usb_wr_protect(lun - LUN_ID_USB); +#else + TRUE; +#endif + + Ctrl_access_unlock(); + + return wr_protect; +} + + +Bool mem_removal(U8 lun) +{ + Bool removal; + + if (!Ctrl_access_lock()) return TRUE; + + removal = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].removal() : +#endif +#if LUN_USB == ENABLE + Lun_usb_removal(); +#else + TRUE; +#endif + + Ctrl_access_unlock(); + + return removal; +} + + +const char *mem_name(U8 lun) +{ + return +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].name : +#endif +#if LUN_USB == ENABLE + LUN_USB_NAME; +#else + NULL; +#endif +} + + +//! @} + + +#if ACCESS_USB == ENABLED + +/*! \name MEM <-> USB Interface + */ +//! @{ + + +Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + memory_start_read_action(nb_sector); + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].usb_read_10(addr, nb_sector) : +#endif + CTRL_FAIL; + memory_stop_read_action(); + + Ctrl_access_unlock(); + + return status; +} + + +Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + memory_start_write_action(nb_sector); + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].usb_write_10(addr, nb_sector) : +#endif + CTRL_FAIL; + memory_stop_write_action(); + + Ctrl_access_unlock(); + + return status; +} + + +//! @} + +#endif // ACCESS_USB == ENABLED + + +#if ACCESS_MEM_TO_RAM == ENABLED + +/*! \name MEM <-> RAM Interface + */ +//! @{ + + +Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + memory_start_read_action(1); + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].mem_2_ram(addr, ram) : +#endif +#if LUN_USB == ENABLE + Lun_usb_mem_2_ram(addr, ram); +#else + CTRL_FAIL; +#endif + memory_stop_read_action(); + + Ctrl_access_unlock(); + + return status; +} + + +Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + memory_start_write_action(1); + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].ram_2_mem(addr, ram) : +#endif +#if LUN_USB == ENABLE + Lun_usb_ram_2_mem(addr, ram); +#else + CTRL_FAIL; +#endif + memory_stop_write_action(); + + Ctrl_access_unlock(); + + return status; +} + + +//! @} + +#endif // ACCESS_MEM_TO_RAM == ENABLED + + +#if ACCESS_STREAM == ENABLED + +/*! \name Streaming MEM <-> MEM Interface + */ +//! @{ + + + #if ACCESS_MEM_TO_MEM == ENABLED + +#include "fat.h" + +Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_addr, U16 nb_sector) +{ +#if (defined __GNUC__) && (defined __AVR32__) + __attribute__((__aligned__(4))) +#elif (defined __ICCAVR32__) + #pragma data_alignment = 4 +#endif + static U8 sector_buf[FS_512B]; + Ctrl_status status = CTRL_GOOD; + + while (nb_sector--) + { + if ((status = memory_2_ram(src_lun, src_addr++, sector_buf)) != CTRL_GOOD) break; + if ((status = ram_2_memory(dest_lun, dest_addr++, sector_buf)) != CTRL_GOOD) break; + } + + return status; +} + + #endif // ACCESS_MEM_TO_MEM == ENABLED + + +Ctrl_status stream_state(U8 id) +{ + return CTRL_GOOD; +} + + +U16 stream_stop(U8 id) +{ + return 0; +} + + +//! @} + +#endif // ACCESS_STREAM == ENABLED diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS/ctrl_access.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS/ctrl_access.h new file mode 100644 index 0000000..358bf65 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/SERVICES/MEMORY/CTRL_ACCESS/ctrl_access.h @@ -0,0 +1,369 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Abstraction layer for memory interfaces. + * + * This module contains the interfaces: + * - MEM <-> USB; + * - MEM <-> RAM; + * - MEM <-> MEM. + * + * This module may be configured and expanded to support the following features: + * - write-protected globals; + * - password-protected data; + * - specific features; + * - etc. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _CTRL_ACCESS_H_ +#define _CTRL_ACCESS_H_ + +#include "compiler.h" +#include "conf_access.h" + + +//! Status returned by CTRL_ACCESS interfaces. +typedef enum +{ + CTRL_GOOD = PASS, //!< Success, memory ready. + CTRL_FAIL = FAIL, //!< An error occurred. + CTRL_NO_PRESENT = FAIL + 1, //!< Memory unplugged. + CTRL_BUSY = FAIL + 2 //!< Memory not initialized or changed. +} Ctrl_status; + + +// FYI: Each Logical Unit Number (LUN) corresponds to a memory. + +// Check LUN defines. +#ifndef LUN_0 + #error LUN_0 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_1 + #error LUN_1 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_2 + #error LUN_2 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_3 + #error LUN_3 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_4 + #error LUN_4 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_5 + #error LUN_5 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_6 + #error LUN_6 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_7 + #error LUN_7 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_USB + #error LUN_USB must be defined as ENABLE or DISABLE in conf_access.h +#endif + +/*! \name LUN IDs + */ +//! @{ +#define LUN_ID_0 (0) //!< First static LUN. +#define LUN_ID_1 (LUN_ID_0 + LUN_0) +#define LUN_ID_2 (LUN_ID_1 + LUN_1) +#define LUN_ID_3 (LUN_ID_2 + LUN_2) +#define LUN_ID_4 (LUN_ID_3 + LUN_3) +#define LUN_ID_5 (LUN_ID_4 + LUN_4) +#define LUN_ID_6 (LUN_ID_5 + LUN_5) +#define LUN_ID_7 (LUN_ID_6 + LUN_6) +#define MAX_LUN (LUN_ID_7 + LUN_7) //!< Number of static LUNs. +#define LUN_ID_USB (MAX_LUN) //!< First dynamic LUN (USB host mass storage). +//! @} + + +// Include LUN header files. +#if LUN_0 == ENABLE + #include LUN_0_INCLUDE +#endif +#if LUN_1 == ENABLE + #include LUN_1_INCLUDE +#endif +#if LUN_2 == ENABLE + #include LUN_2_INCLUDE +#endif +#if LUN_3 == ENABLE + #include LUN_3_INCLUDE +#endif +#if LUN_4 == ENABLE + #include LUN_4_INCLUDE +#endif +#if LUN_5 == ENABLE + #include LUN_5_INCLUDE +#endif +#if LUN_6 == ENABLE + #include LUN_6_INCLUDE +#endif +#if LUN_7 == ENABLE + #include LUN_7_INCLUDE +#endif +#if LUN_USB == ENABLE + #include LUN_USB_INCLUDE +#endif + + +// Check the configuration of write protection in conf_access.h. +#ifndef GLOBAL_WR_PROTECT + #error GLOBAL_WR_PROTECT must be defined as ENABLED or DISABLED in conf_access.h +#endif + + +#if GLOBAL_WR_PROTECT == ENABLED + +//! Write protect. +extern Bool g_wr_protect; + +#endif + + +/*! \name Control Interface + */ +//! @{ + +#ifdef FREERTOS_USED + +/*! \brief Initializes the LUN access locker. + * + * \return \c TRUE if the locker was successfully initialized, else \c FALSE. + */ +extern Bool ctrl_access_init(void); + +#endif // FREERTOS_USED + +/*! \brief Returns the number of LUNs. + * + * \return Number of LUNs in the system. + */ +extern U8 get_nb_lun(void); + +/*! \brief Returns the current LUN. + * + * \return Current LUN. + * + * \todo Implement. + */ +extern U8 get_cur_lun(void); + +/*! \brief Tests the memory state and initializes the memory if required. + * + * The TEST UNIT READY SCSI primary command allows an application client to poll + * a LUN until it is ready without having to allocate memory for returned data. + * + * This command may be used to check the media status of LUNs with removable + * media. + * + * \param lun Logical Unit Number. + * + * \return Status. + */ +extern Ctrl_status mem_test_unit_ready(U8 lun); + +/*! \brief Returns the address of the last valid sector (512 bytes) in the + * memory. + * + * \param lun Logical Unit Number. + * \param u32_nb_sector Pointer to the address of the last valid sector. + * + * \return Status. + */ +extern Ctrl_status mem_read_capacity(U8 lun, U32 *u32_nb_sector); + +/*! \brief Returns the size of the physical sector. + * + * \param lun Logical Unit Number. + * + * \return Sector size (unit: 512 bytes). + */ +extern U8 mem_sector_size(U8 lun); + +/*! \brief Returns the write-protection state of the memory. + * + * \param lun Logical Unit Number. + * + * \return \c TRUE if the memory is write-protected, else \c FALSE. + * + * \note Only used by removable memories with hardware-specific write + * protection. + */ +extern Bool mem_wr_protect(U8 lun); + +/*! \brief Tells whether the memory is removable. + * + * \param lun Logical Unit Number. + * + * \return \c TRUE if the memory is removable, else \c FALSE. + */ +extern Bool mem_removal(U8 lun); + +/*! \brief Returns a pointer to the LUN name. + * + * \param lun Logical Unit Number. + * + * \return Pointer to the LUN name string. + */ +extern const char *mem_name(U8 lun); + +//! @} + + +#if ACCESS_USB == ENABLED + +/*! \name MEM <-> USB Interface + */ +//! @{ + +/*! \brief Tranfers data from the memory to USB. + * + * \param lun Logical Unit Number. + * \param addr Address of first memory sector to read. + * \param nb_sector Number of sectors to transfer. + * + * \return Status. + */ +extern Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector); + +/*! \brief Tranfers data from USB to the memory. + * + * \param lun Logical Unit Number. + * \param addr Address of first memory sector to write. + * \param nb_sector Number of sectors to transfer. + * + * \return Status. + */ +extern Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector); + +//! @} + +#endif // ACCESS_USB == ENABLED + + +#if ACCESS_MEM_TO_RAM == ENABLED + +/*! \name MEM <-> RAM Interface + */ +//! @{ + +/*! \brief Copies 1 data sector from the memory to RAM. + * + * \param lun Logical Unit Number. + * \param addr Address of first memory sector to read. + * \param ram Pointer to RAM buffer to write. + * + * \return Status. + */ +extern Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram); + +/*! \brief Copies 1 data sector from RAM to the memory. + * + * \param lun Logical Unit Number. + * \param addr Address of first memory sector to write. + * \param ram Pointer to RAM buffer to read. + * + * \return Status. + */ +extern Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram); + +//! @} + +#endif // ACCESS_MEM_TO_RAM == ENABLED + + +#if ACCESS_STREAM == ENABLED + +/*! \name Streaming MEM <-> MEM Interface + */ +//! @{ + +//! Erroneous streaming data transfer ID. +#define ID_STREAM_ERR 0xFF + + #if ACCESS_MEM_TO_MEM == ENABLED + +/*! \brief Copies data from one memory to another. + * + * \param src_lun Source Logical Unit Number. + * \param src_addr Source address of first memory sector to read. + * \param dest_lun Destination Logical Unit Number. + * \param dest_addr Destination address of first memory sector to write. + * \param nb_sector Number of sectors to copy. + * + * \return Status. + */ +extern Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_addr, U16 nb_sector); + + #endif // ACCESS_MEM_TO_MEM == ENABLED + +/*! \brief Returns the state of a streaming data transfer. + * + * \param id Transfer ID. + * + * \return Status. + * + * \todo Implement. + */ +extern Ctrl_status stream_state(U8 id); + +/*! \brief Stops a streaming data transfer. + * + * \param id Transfer ID. + * + * \return Number of remaining sectors. + * + * \todo Implement. + */ +extern U16 stream_stop(U8 id); + +//! @} + +#endif // ACCESS_STREAM == ENABLED + + +#endif // _CTRL_ACCESS_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/debug.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/debug.c new file mode 100644 index 0000000..c7c0a03 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/debug.c @@ -0,0 +1,119 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Macros and functions dedicated to debug purposes. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include "compiler.h" +#include "debug.h" + + +#if (defined __GNUC__) +# include "malloc.h" + +U32 get_heap_curr_used_size( void ) +{ + struct mallinfo my_info=mallinfo(); + return my_info.uordblks; +} + +U32 get_heap_total_used_size( void ) +{ + struct mallinfo my_info=mallinfo(); + return my_info.arena; +} +#endif + +U32 get_heap_free_size( void ) +{ + U32 high_mark= AVR32_SRAM_SIZE; + U32 low_mark = 0; + U32 size ; + void* p_mem; + + size = (high_mark + low_mark)/2; + + do + { + p_mem = malloc(size); + if( p_mem != NULL) + { // Can allocate memory + free(p_mem); + low_mark = size; + } + else + { // Can not allocate memory + high_mark = size; + } + + size = (high_mark + low_mark)/2; + } + while( (high_mark-low_mark) >1 ); + + return size; +} + +static void* round_trace_pbuf; +static U32 round_trace_size; + +void uc3_round_trace_init(void* buf, U32 size) +{ + round_trace_pbuf = buf; + (*(U32*)round_trace_pbuf)=(U32)buf+4; + round_trace_size = size; +} + +void uc3_round_trace(U32 val) +{ + //Disable_global_interrupt(); + + U32* p_wr = (U32*)(*(U32*)round_trace_pbuf); + *p_wr = val; + p_wr++; + if( ((U32)p_wr % round_trace_size) ==0 ) + p_wr= (U32*)round_trace_pbuf+1; + *p_wr = 0xdeadbeef; + *(U32*)round_trace_pbuf = (U32)p_wr; + + //Enable_global_interrupt(); +} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/debug.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/debug.h new file mode 100644 index 0000000..a832d7c --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/debug.h @@ -0,0 +1,116 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Macros and functions dedicated to debug purposes. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _DEBUG_H_ +#define _DEBUG_H_ + +#include "stringz.h" + +/*! \brief These macros are used to add traces memory. + * + * First, initialise the trace with Uc3_trace_init(pointer), giving the start address + * of the memory location where will be stored the trace. + * Use Uc3_trace(something) to store "something" into the memory. The end of the trace + * is signaled by the "0xdeadbeef" pattern. + */ +#define Uc3_trace_init(debug_addr) \ + *(U32*)(debug_addr)=debug_addr+4 + +#define Uc3_trace(debug_addr, x) \ + *(U32*)(*(U32*)(debug_addr) ) = (U32)(x) ;\ + *(U32*)(*(U32*)(debug_addr)+4) = 0xdeadbeef ;\ + *(U32*)(debug_addr ) = *(U32*)(debug_addr)+4 + +/*! \brief This macro is used to insert labels into assembly output. + * + */ +#define Insert_label(name) \ + __asm__ __volatile__ (STRINGZ(name)":"); + +#if (defined __GNUC__) +/*! \brief Returns the number of total of used bytes allocated from the HEAP. + * + * \retval total number of used bytes. + */ +U32 get_heap_total_used_size( void ); + +/*! \brief Returns the number of bytes currently used from the HEAP. + * + * \retval total number of used bytes. + */ +U32 get_heap_curr_used_size( void ); +#endif + +/*! \brief Returns the number of free bytes in the HEAP. + * + * This funtion tries to allocate the maximum number of bytes by dichotomical method. + * + * \retval number of free bytes. + */ +extern U32 get_heap_free_size( void ); + +/*! \name Traces function using a round buffer + */ +//! @{ + +/*! \brief Initialize the trace using a round buffer. + * + * \param buf Base address of the buffer used for the trace. + * \param size Size of the round buffer. Must be a power of 2. + */ +void uc3_round_trace_init(void* buf, U32 size); + +/*! \brief Trace a data in the round buffer. + * + * The end of the trace is signaled by the "0xdeadbeef" pattern. + * \param val Data to trace; + */ +void uc3_round_trace(U32 val); + +//! @} + + +#endif // _DEBUG_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/print_funcs.c b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/print_funcs.c new file mode 100644 index 0000000..99e9274 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/print_funcs.c @@ -0,0 +1,215 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Strings and integers print module for debug purposes. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include "compiler.h" +#include "gpio.h" +#include "usart.h" +#include "print_funcs.h" + + +//! ASCII representation of hexadecimal digits. +static const char HEX_DIGITS[16] = "0123456789ABCDEF"; + + +void init_dbg_rs232(long pba_hz) +{ + init_dbg_rs232_ex(DBG_USART_BAUDRATE, pba_hz); +} + + +void init_dbg_rs232_ex(unsigned long baudrate, long pba_hz) +{ + static const gpio_map_t DBG_USART_GPIO_MAP = + { + {DBG_USART_RX_PIN, DBG_USART_RX_FUNCTION}, + {DBG_USART_TX_PIN, DBG_USART_TX_FUNCTION} + }; + + // Options for debug USART. + usart_options_t dbg_usart_options = + { + .baudrate = baudrate, + .charlength = 8, + .paritytype = USART_NO_PARITY, + .stopbits = USART_1_STOPBIT, + .channelmode = USART_NORMAL_CHMODE + }; + + // Setup GPIO for debug USART. + gpio_enable_module(DBG_USART_GPIO_MAP, + sizeof(DBG_USART_GPIO_MAP) / sizeof(DBG_USART_GPIO_MAP[0])); + + // Initialize it in RS232 mode. + usart_init_rs232(DBG_USART, &dbg_usart_options, pba_hz); +} + + +void print_dbg(const char *str) +{ + // Redirection to the debug USART. + print(DBG_USART, str); +} + + +void print_dbg_char(int c) +{ + // Redirection to the debug USART. + print_char(DBG_USART, c); +} + + +void print_dbg_ulong(unsigned long n) +{ + // Redirection to the debug USART. + print_ulong(DBG_USART, n); +} + + +void print_dbg_char_hex(unsigned char n) +{ + // Redirection to the debug USART. + print_char_hex(DBG_USART, n); +} + + +void print_dbg_short_hex(unsigned short n) +{ + // Redirection to the debug USART. + print_short_hex(DBG_USART, n); +} + + +void print_dbg_hex(unsigned long n) +{ + // Redirection to the debug USART. + print_hex(DBG_USART, n); +} + + +void print(volatile avr32_usart_t *usart, const char *str) +{ + // Invoke the USART driver to transmit the input string with the given USART. + usart_write_line(usart, str); +} + + +void print_char(volatile avr32_usart_t *usart, int c) +{ + // Invoke the USART driver to transmit the input character with the given USART. + usart_putchar(usart, c); +} + + +void print_ulong(volatile avr32_usart_t *usart, unsigned long n) +{ + char tmp[11]; + int i = sizeof(tmp) - 1; + + // Convert the given number to an ASCII decimal representation. + tmp[i] = '\0'; + do + { + tmp[--i] = '0' + n % 10; + n /= 10; + } while (n); + + // Transmit the resulting string with the given USART. + print(usart, tmp + i); +} + + +void print_char_hex(volatile avr32_usart_t *usart, unsigned char n) +{ + char tmp[3]; + int i; + + // Convert the given number to an ASCII hexadecimal representation. + tmp[2] = '\0'; + for (i = 1; i >= 0; i--) + { + tmp[i] = HEX_DIGITS[n & 0xF]; + n >>= 4; + } + + // Transmit the resulting string with the given USART. + print(usart, tmp); +} + + +void print_short_hex(volatile avr32_usart_t *usart, unsigned short n) +{ + char tmp[5]; + int i; + + // Convert the given number to an ASCII hexadecimal representation. + tmp[4] = '\0'; + for (i = 3; i >= 0; i--) + { + tmp[i] = HEX_DIGITS[n & 0xF]; + n >>= 4; + } + + // Transmit the resulting string with the given USART. + print(usart, tmp); +} + + +void print_hex(volatile avr32_usart_t *usart, unsigned long n) +{ + char tmp[9]; + int i; + + // Convert the given number to an ASCII hexadecimal representation. + tmp[8] = '\0'; + for (i = 7; i >= 0; i--) + { + tmp[i] = HEX_DIGITS[n & 0xF]; + n >>= 4; + } + + // Transmit the resulting string with the given USART. + print(usart, tmp); +} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/print_funcs.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/print_funcs.h new file mode 100644 index 0000000..38f931d --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/DEBUG/print_funcs.h @@ -0,0 +1,294 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Strings and integers print module for debug purposes. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _PRINT_FUNCS_H_ +#define _PRINT_FUNCS_H_ + +#include <avr32/io.h> +#include "board.h" + + +/*! \name USART Settings for the Debug Module + */ +//! @{ +#if BOARD == EVK1100 +# define DBG_USART (&AVR32_USART1) +# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION +# define DBG_USART_BAUDRATE 57600 +#elif BOARD == EVK1101 +# define DBG_USART (&AVR32_USART1) +# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION +# define DBG_USART_BAUDRATE 57600 +#elif BOARD == UC3C_EK +# define DBG_USART (&AVR32_USART2) +# define DBG_USART_RX_PIN AVR32_USART2_RXD_0_1_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART2_RXD_0_1_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART2_TXD_0_1_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART2_TXD_0_1_FUNCTION +# define DBG_USART_BAUDRATE 57600 +#elif BOARD == EVK1104 +# define DBG_USART (&AVR32_USART1) +# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION +# define DBG_USART_BAUDRATE 57600 +#elif BOARD == EVK1105 +# define DBG_USART (&AVR32_USART0) +# define DBG_USART_RX_PIN AVR32_USART0_RXD_0_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART0_RXD_0_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART0_TXD_0_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART0_TXD_0_0_FUNCTION +# define DBG_USART_BAUDRATE 57600 +#elif BOARD == STK1000 +# define DBG_USART (&AVR32_USART1) +# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_FUNCTION +# define DBG_USART_BAUDRATE 115200 +#elif BOARD == NGW100 +# define DBG_USART (&AVR32_USART1) +# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_FUNCTION +# define DBG_USART_BAUDRATE 115200 +#elif BOARD == STK600_RCUC3L0 +# define DBG_USART (&AVR32_USART1) +# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_1_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_1_FUNCTION +// For the RX pin, connect STK600.PORTE.PE3 to STK600.RS232 SPARE.RXD +# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_1_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_1_FUNCTION +// For the TX pin, connect STK600.PORTE.PE2 to STK600.RS232 SPARE.TXD +# define DBG_USART_BAUDRATE 57600 +# define DBG_USART_CLOCK_MASK AVR32_USART1_CLK_PBA +#elif BOARD == UC3L_EK +# define DBG_USART (&AVR32_USART3) +# define DBG_USART_RX_PIN AVR32_USART3_RXD_0_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART3_RXD_0_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART3_TXD_0_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART3_TXD_0_0_FUNCTION +# define DBG_USART_BAUDRATE 57600 +# define DBG_USART_CLOCK_MASK AVR32_USART3_CLK_PBA +#elif BOARD == ARDUINO +# define DBG_USART (&AVR32_USART1) +# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN +# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION +# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN +# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION +# define DBG_USART_BAUDRATE 57600 +# define DBG_USART_CLOCK_MASK AVR32_USART1_CLK_PBA +#endif + +#if !defined(DBG_USART) || \ + !defined(DBG_USART_RX_PIN) || \ + !defined(DBG_USART_RX_FUNCTION) || \ + !defined(DBG_USART_TX_PIN) || \ + !defined(DBG_USART_TX_FUNCTION) || \ + !defined(DBG_USART_BAUDRATE) +# error The USART configuration to use for debug on your board is missing +#endif +//! @} + +/*! \name VT100 Common Commands + */ +//! @{ +#define CLEARSCR "\x1B[2J\x1B[;H" //!< Clear screen. +#define CLEAREOL "\x1B[K" //!< Clear end of line. +#define CLEAREOS "\x1B[J" //!< Clear end of screen. +#define CLEARLCR "\x1B[0K" //!< Clear line cursor right. +#define CLEARLCL "\x1B[1K" //!< Clear line cursor left. +#define CLEARELN "\x1B[2K" //!< Clear entire line. +#define CLEARCDW "\x1B[0J" //!< Clear cursor down. +#define CLEARCUP "\x1B[1J" //!< Clear cursor up. +#define GOTOYX "\x1B[%.2d;%.2dH" //!< Set cursor to (y, x). +#define INSERTMOD "\x1B[4h" //!< Insert mode. +#define OVERWRITEMOD "\x1B[4l" //!< Overwrite mode. +#define DELAFCURSOR "\x1B[K" //!< Erase from cursor to end of line. +#define CRLF "\r\n" //!< Carriage Return + Line Feed. +//! @} + +/*! \name VT100 Cursor Commands + */ +//! @{ +#define CURSON "\x1B[?25h" //!< Show cursor. +#define CURSOFF "\x1B[?25l" //!< Hide cursor. +//! @} + +/*! \name VT100 Character Commands + */ +//! @{ +#define NORMAL "\x1B[0m" //!< Normal. +#define BOLD "\x1B[1m" //!< Bold. +#define UNDERLINE "\x1B[4m" //!< Underline. +#define BLINKING "\x1B[5m" //!< Blink. +#define INVVIDEO "\x1B[7m" //!< Inverse video. +//! @} + +/*! \name VT100 Color Commands + */ +//! @{ +#define CL_BLACK "\033[22;30m" //!< Black. +#define CL_RED "\033[22;31m" //!< Red. +#define CL_GREEN "\033[22;32m" //!< Green. +#define CL_BROWN "\033[22;33m" //!< Brown. +#define CL_BLUE "\033[22;34m" //!< Blue. +#define CL_MAGENTA "\033[22;35m" //!< Magenta. +#define CL_CYAN "\033[22;36m" //!< Cyan. +#define CL_GRAY "\033[22;37m" //!< Gray. +#define CL_DARKGRAY "\033[01;30m" //!< Dark gray. +#define CL_LIGHTRED "\033[01;31m" //!< Light red. +#define CL_LIGHTGREEN "\033[01;32m" //!< Light green. +#define CL_YELLOW "\033[01;33m" //!< Yellow. +#define CL_LIGHTBLUE "\033[01;34m" //!< Light blue. +#define CL_LIGHTMAGENTA "\033[01;35m" //!< Light magenta. +#define CL_LIGHTCYAN "\033[01;36m" //!< Light cyan. +#define CL_WHITE "\033[01;37m" //!< White. +//! @} + + +/*! \brief Sets up DBG_USART with 8N1 at DBG_USART_BAUDRATE. + * + * \param pba_hz PBA clock frequency (Hz). + */ +extern void init_dbg_rs232(long pba_hz); + +/*! \brief Sets up DBG_USART with 8N1 at a given baud rate. + * + * \param baudrate Baud rate to set DBG_USART to. + * \param pba_hz PBA clock frequency (Hz). + */ +extern void init_dbg_rs232_ex(unsigned long baudrate, long pba_hz); + +/*! \brief Prints a string of characters to DBG_USART. + * + * \param str The string of characters to print. + */ +extern void print_dbg(const char *str); + +/*! \brief Prints a character to DBG_USART. + * + * \param c The character to print. + */ +extern void print_dbg_char(int c); + +/*! \brief Prints an integer to DBG_USART in a decimal representation. + * + * \param n The integer to print. + */ +extern void print_dbg_ulong(unsigned long n); + +/*! \brief Prints a char to DBG_USART in an hexadecimal representation. + * + * \param n The char to print. + */ +extern void print_dbg_char_hex(unsigned char n); + +/*! \brief Prints a short integer to DBG_USART in an hexadecimal representation. + * + * \param n The short integer to print. + */ +extern void print_dbg_short_hex(unsigned short n); + +/*! \brief Prints an integer to DBG_USART in an hexadecimal representation. + * + * \param n The integer to print. + */ +extern void print_dbg_hex(unsigned long n); + +/*! \brief Prints a string of characters to a given USART. + * + * \param usart Base address of the USART instance to print to. + * \param str The string of characters to print. + */ +extern void print(volatile avr32_usart_t *usart, const char *str); + +/*! \brief Prints a character to a given USART. + * + * \param usart Base address of the USART instance to print to. + * \param c The character to print. + */ +extern void print_char(volatile avr32_usart_t *usart, int c); + +/*! \brief Prints an integer to a given USART in a decimal representation. + * + * \param usart Base address of the USART instance to print to. + * \param n The integer to print. + */ +extern void print_ulong(volatile avr32_usart_t *usart, unsigned long n); + +/*! \brief Prints a char to a given USART in an hexadecimal representation. + * + * \param usart Base address of the USART instance to print to. + * \param n The char to print. + */ +extern void print_char_hex(volatile avr32_usart_t *usart, unsigned char n); + +/*! \brief Prints a short integer to a given USART in an hexadecimal + * representation. + * + * \param usart Base address of the USART instance to print to. + * \param n The short integer to print. + */ +extern void print_short_hex(volatile avr32_usart_t *usart, unsigned short n); + +/*! \brief Prints an integer to a given USART in an hexadecimal representation. + * + * \param usart Base address of the USART instance to print to. + * \param n The integer to print. + */ +extern void print_hex(volatile avr32_usart_t *usart, unsigned long n); + + +#endif // _PRINT_FUNCS_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_cpu.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_cpu.h new file mode 100644 index 0000000..e3ebea7 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_cpu.h @@ -0,0 +1,63 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief NEWLIB_ADDONS CPU include file for AVR32. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef __AVR32_NEWLIB_ADDONS_CPU_H__ +#define __AVR32_NEWLIB_ADDONS_CPU_H__ + +#include <_ansi.h> + +_BEGIN_STD_C + +#define CPU_HZ get_cpu_hz() + +void udelay(unsigned long usec); +void set_cpu_hz(unsigned int clk_hz); +unsigned int get_cpu_hz(); + +_END_STD_C + +#endif diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_exceptions.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_exceptions.h new file mode 100644 index 0000000..31caf13 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_exceptions.h @@ -0,0 +1,120 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief NEWLIB_ADDONS exceptions include file for AVR32. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef __AVR32_NEWLIB_ADDONS_EXCEPTIONS_H__ +#define __AVR32_NEWLIB_ADDONS_EXCEPTIONS_H__ + +#include <_ansi.h> + +_BEGIN_STD_C + +/* + Exception vector offsets +*/ +#define EVBA_UNRECOVERABLE 0x000 +#define EVBA_TLB_MULTIPLE 0x004 +#define EVBA_BUS_ERROR_DATA 0x008 +#define EVBA_BUS_ERROR_INSTR 0x00C +#define EVBA_NMI 0x010 +#define EVBA_INSTR_ADDR 0x014 +#define EVBA_ITLB_MISS 0x050 +#define EVBA_ITLB_PROT 0x018 +#define EVBA_BREAKPOINT 0x01C +#define EVBA_ILLEGAL_OPCODE 0x020 +#define EVBA_UNIMPLEMENTED 0x024 +#define EVBA_PRIVILEGE_VIOL 0x028 +#define EVBA_FLOATING_POINT 0x02C +#define EVBA_COP_ABSENT 0x030 +#define EVBA_SCALL 0x100 +#define EVBA_DATA_ADDR_R 0x034 +#define EVBA_DATA_ADDR_W 0x038 +#define EVBA_DTLB_MISS_R 0x060 +#define EVBA_DTLB_MISS_W 0x070 +#define EVBA_DTLB_PROT_R 0x03C +#define EVBA_DTLB_PROT_W 0x040 +#define EVBA_DTLB_MODIFIED 0x044 + + +/* + Define the form of the function used when registering exceptions. + The function should return the address which the exception should + return to after the exception processing. +*/ + +typedef unsigned int (*__exception_handler)(int /*evba_offset*/, int /*return address*/); + +/* + Define the form of the function used when registering a scall handler. +*/ + +typedef void (*__scall_handler)(int /*code*/, int /*p1*/, int /*p2*/ + , int /*p3*/, int /*p4*/); + +/* + Function for registering an exception handler for the exception with + offset given by evba_offset. +*/ +void _register_exception_handler(__exception_handler handler, int evba_offset); + +/* + Function for registering a scall handler which can be a arbirary + function which uses r8-r12 for parameters. +*/ +void _register_scall_handler(__scall_handler handler); + +/* + Initialize exceptions. Must be called before registering exception handlers + and needed to enable exceptions. 'evba' is the pointer to the exception + vector. 'handler_table' is a pointer to an array where the pointers to + the exception handlers are stored. This array must be at least 0x104 bytes + and word aligned. +*/ +void init_exceptions(void *evba, void *handler_table); + +_END_STD_C + +#endif diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_interrupts.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_interrupts.h new file mode 100644 index 0000000..76d81f7 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_interrupts.h @@ -0,0 +1,82 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief NEWLIB_ADDONS interrupts include file for AVR32. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef __AVR32_NEWLIB_ADDONS_INTERRUPTS_H__ +#define __AVR32_NEWLIB_ADDONS_INTERRUPTS_H__ + +#include <_ansi.h> + +_BEGIN_STD_C + +#define INT_GRPS 64 +#define INT_LINES 32 +#define INTPR_BASE (__intc_base__ + 0x0000) +#define INTREQ_BASE (__intc_base__ + 64*4) +#define INTCAUSE_BASE (__intc_base__ + 2*64*4) + +//Register offsets +#define INTLEVEL 30 +#define AUTOVECTOR 0 +#define AUTOVECTOR_BITS 14 + +//Priorities +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 + + +typedef void (*__newlib_int_handler)(int /* int_grp*/, void */*user_handle*/); + +__newlib_int_handler register_interrupt(__newlib_int_handler handler, int int_grp, int line, int priority, + .../* void *user_handle*/); +void init_interrupts(); +void set_interrupts_base(void *base); + +_END_STD_C + +#endif diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_io.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_io.h new file mode 100644 index 0000000..a725769 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_io.h @@ -0,0 +1,174 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief NEWLIB_ADDONS miscellaneous macros include file for AVR32. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef __AVR32_NEWLIB_ADDONS_IO_H__ +#define __AVR32_NEWLIB_ADDONS_IO_H__ + +#include <_ansi.h> + +_BEGIN_STD_C + +typedef char u8; +typedef unsigned int u32; + +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + +/* As long as I/O is only performed in P4 (or possibly P3), we're safe */ +#define writeb(v,a) __raw_writeb(v,a) +#define writew(v,a) __raw_writew(v,a) +#define writel(v,a) __raw_writel(v,a) + +#define readb(a) __raw_readb(a) +#define readw(a) __raw_readw(a) +#define readl(a) __raw_readl(a) + +/* Memory segments when segmentation is enabled */ +#define P0SEG 0x00000000 +#define P1SEG 0x80000000 +#define P2SEG 0xa0000000 +#define P3SEG 0xc0000000 +#define P4SEG 0xe0000000 + +/* Returns the privileged segment base of a given address */ +#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) + +/* Returns the physical address of a PnSEG (n=1,2) address */ +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) + +/* + * Map an address to a certain privileged segment + */ +#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) +#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) +#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) +#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) + + +#define cached(addr) P1SEGADDR(addr) +#define uncached(addr) P2SEGADDR(addr) +#define physaddr(addr) PHYSADDR(addr) + +#define BF(field, value) \ + ({ union { \ + struct { \ + unsigned : 32 - field ## _OFFSET - field ## _SIZE ; \ + unsigned long __val: field ## _SIZE ; \ + }; \ + unsigned long __ul; \ + } __tmp; \ + __tmp.__ul = 0; \ + __tmp.__val = value; \ + __tmp.__ul;}) + +#define BF_D(field, value) \ + ({ union { \ + struct { \ + unsigned long long : 64 - field ## _OFFSET - field ## _SIZE ; \ + unsigned long long __val: field ## _SIZE ; \ + }; \ + unsigned long long __ul; \ + } __tmp; \ + __tmp.__ul = 0; \ + __tmp.__val = value; \ + __tmp.__ul;}) + +#define BFINS(var, field, value) \ + { union {\ + struct { \ + unsigned : 32 - field ## _OFFSET - field ## _SIZE ; \ + unsigned long __val: field ## _SIZE ; \ + }; \ + unsigned long __ul; \ + } __tmp; \ + __tmp.__ul = var; \ + __tmp.__val = value; \ + var = __tmp.__ul;} + +#define BFEXT(var, field) \ + ({ union {\ + struct { \ + unsigned : 32 - field ## _OFFSET - field ## _SIZE ; \ + unsigned long __val: field ## _SIZE ; \ + }; \ + unsigned long __ul; \ + } __tmp; \ + __tmp.__ul = var; \ + __tmp.__val; }) + +#define BFINS_D(var, field, value) \ + { union {\ + struct { \ + unsigned long long : 64 - field ## _OFFSET - field ## _SIZE ; \ + unsigned long long __val: field ## _SIZE ; \ + }; \ + unsigned long long __ul; \ + } __tmp; \ + __tmp.__ul = var; \ + __tmp.__val = value; \ + var = __tmp.__ul;} + +#define BFEXT_D(var, field) \ + ({ union {\ + struct { \ + unsigned long long : 64 - field ## _OFFSET - field ## _SIZE ; \ + unsigned long long __val: field ## _SIZE ; \ + }; \ + unsigned long long __ul; \ + } __tmp; \ + __tmp.__ul = var; \ + __tmp.__val; }) + + +_END_STD_C + +#endif diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_usart.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_usart.h new file mode 100644 index 0000000..6c4697d --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_usart.h @@ -0,0 +1,208 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief NEWLIB_ADDONS USART include file for AVR32. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef __AVR32_NEWLIB_ADDONS_USART_H__ +#define __AVR32_NEWLIB_ADDONS_USART_H__ + +#include <_ansi.h> + +#include "nlao_io.h" + +_BEGIN_STD_C + +struct usart3 { + volatile u32 us_cr; + volatile u32 us_mr; + volatile u32 us_ier; + volatile u32 us_idr; + volatile u32 us_imr; + volatile u32 us_csr; + volatile u32 us_rhr; + volatile u32 us_thr; + volatile u32 us_brgr; + volatile u32 us_rtor; + volatile u32 us_ttgr; + volatile u32 us_reserved[5]; + volatile u32 us_fidi; + volatile u32 us_ner; + volatile u32 us_xxr; + volatile u32 us_if; +}; + +/* Register offsets */ +#define US_CR 0x0000 +#define US_MR 0x0004 +#define US_IER 0x0008 +#define US_IDR 0x000c +#define US_IMR 0x0010 +#define US_CSR 0x0014 +#define US_RHR 0x0018 +#define US_THR 0x001c +#define US_BRGR 0x0020 +#define US_RTOR 0x0024 +#define US_TTGR 0x0028 + +#define US_FIDI 0x0040 +#define US_NER 0x0044 +#define US_XXR 0x0048 +#define US_IF 0x004c + +#define US_RPR 0x0100 +#define US_RCR 0x0104 +#define US_TPR 0x0108 +#define US_TCR 0x010c +#define US_RNPR 0x0110 +#define US_RNCR 0x0114 +#define US_TNPR 0x0118 +#define US_TNCR 0x011c +#define US_PTCR 0x0120 +#define US_PTSR 0x0124 + + + + +/* USART3 Control Register */ +#define US_CR_RSTRX (1 << 2) +#define US_CR_RSTTX (1 << 3) +#define US_CR_RXEN (1 << 4) +#define US_CR_RXDIS (1 << 5) +#define US_CR_TXEN (1 << 6) +#define US_CR_TXDIS (1 << 7) +#define US_CR_RSTSTA (1 << 8) +#define US_CR_STTBRK (1 << 9) +#define US_CR_STPBRK (1 << 10) + +#define US_CR_DTREN (1 << 16) +#define US_CR_DTRDIS (1 << 17) +#define US_CR_RTSEN (1 << 18) +#define US_CR_RTSDIS (1 << 19) + +/* USART3 Mode Register */ +#define US_MR_MODE (15 << 0) +#define US_MR_MODE_NORMAL ( 0 << 0) +#define US_MR_MODE_HWFLOW ( 2 << 0) +#define US_MR_CLKS ( 3 << 4) +#define US_MR_CLKS_CLOCK ( 0 << 4) +#define US_MR_CLKS_FDIV1 ( 1 << 4) +#define US_MR_CLKS_SLOW ( 2 << 4) +#define US_MR_CLKS_EXT ( 3 << 4) +#define US_MR_CHRL_5BITS ( 0 << 6) +#define US_MR_CHRL_6BITS ( 1 << 6) +#define US_MR_CHRL_7BITS ( 2 << 6) +#define US_MR_CHRL_8BITS ( 3 << 6) +#define US_MR_SYNC ( 1 << 8) +#define US_MR_PAR_EVEN ( 0 << 9) +#define US_MR_PAR_ODD ( 1 << 9) +#define US_MR_PAR_SPACE ( 2 << 9) +#define US_MR_PAR_MARK ( 3 << 9) +#define US_MR_PAR_NONE ( 4 << 9) +#define US_MR_PAR_MDROP ( 6 << 9) +#define US_MR_NBSTOP_1BIT ( 0 << 12) +#define US_MR_NBSTOP_1_5BIT ( 1 << 12) +#define US_MR_NBSTOP_2BITS ( 2 << 12) +#define US_MR_OVER ( 1 << 19) +#define US_MR_OVER_X16 ( 0 << 19) +#define US_MR_OVER_X8 ( 1 << 19) + +/* USART3 Channel Status Register */ +#define US_CSR_RXRDY (1 << 0) +#define US_CSR_TXRDY (1 << 1) +#define US_CSR_RXBRK (1 << 2) +#define US_CSR_ENDRX (1 << 3) +#define US_CSR_ENDTX (1 << 4) + + +#define US_CSR_OVRE (1 << 5) +#define US_CSR_FRAME (1 << 6) +#define US_CSR_PARE (1 << 7) + +#define US_CSR_TXEMPTY (1 << 9) + +#define US_CSR_TXBUFE (1 << 11) +#define US_CSR_RXBUFF (1 << 12) +#define US_CSR_RIIC (1 << 16) +#define US_CSR_DSRIC (1 << 17) +#define US_CSR_DCDIC (1 << 18) +#define US_CSR_CTSIC (1 << 19) +#define US_CSR_RI (1 << 20) +#define US_CSR_DSR (1 << 21) +#define US_CSR_DCD (1 << 22) +#define US_CSR_CTS (1 << 23) + +/* USART3 Baud Rate Generator Register */ +#define US_BRGR_CD_OFFSET 0 +#define US_BRGR_FP_OFFSET 16 + +#define US_BRGR_CD_SIZE 16 +#define US_BRGR_FP_SIZE 3 + +#define US_BRGR_CD (0xFFFF << 0) +#define US_BRGR_FP ( 7 << 16) + +/*USART3 PDC Transfer Control Register */ +#define US_PTCR_RXTEN (1 << 0) +#define US_PTCR_RXTDIS (1 << 1) +#define US_PTCR_TXTEN (1 << 8) +#define US_PTCR_TXTDIS (1 << 9) + +/*USART3 PDC Transfer Status Register */ +#define US_PTSR_RXTEN (1 << 0) +#define US_PTSR_TXTEN (1 << 8) + + +int usart_init(int baudrate); +void usart_putc(char c); +void usart_puts(const char *s); +int usart_getc(void); +int usart_tstc(void); +void usart_setbrg(int baudrate, int cpu_clock); +void set_usart_base(void *usart_base); + + +_END_STD_C + +#endif /* MERLIN_USART3_H */ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/libnewlib_addons-at32ucr2-speed_opt.a b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/libnewlib_addons-at32ucr2-speed_opt.a Binary files differnew file mode 100644 index 0000000..aa673ec --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/libnewlib_addons-at32ucr2-speed_opt.a diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds new file mode 100644 index 0000000..59152ac --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds @@ -0,0 +1,266 @@ +/****************************************************************************** + * AVR32 AT32UC3A0512 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3A0512 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00080000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM_ALIGN PT_NULL; + INTRAM_AT_FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM_ALIGN + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .ramtext : { *(.ramtext .ramtext.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .ddalign : { . = ALIGN(8); } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .balign : { . = ALIGN(8); PROVIDE(_edata = .); } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds new file mode 100644 index 0000000..a5926d8 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds @@ -0,0 +1,266 @@ +/****************************************************************************** + * AVR32 AT32UC3A1256 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3A1256 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM_ALIGN PT_NULL; + INTRAM_AT_FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM_ALIGN + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .ramtext : { *(.ramtext .ramtext.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .ddalign : { . = ALIGN(8); } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .balign : { . = ALIGN(8); PROVIDE(_edata = .); } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/mrepeat.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/mrepeat.h new file mode 100644 index 0000000..41163b6 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/mrepeat.h @@ -0,0 +1,328 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor macro repeating utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _MREPEAT_H_ +#define _MREPEAT_H_ + +#include "preprocessor.h" + + +//! Maximal number of repetitions supported by MREPEAT. +#define MREPEAT_LIMIT 256 + +/*! \brief Macro repeat. + * + * This macro represents a horizontal repetition construct. + * + * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT. + * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with + * the current repetition number and the auxiliary data argument. + * \param data Auxiliary data passed to macro. + * + * \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt> + */ +#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data) + +#define MREPEAT0( macro, data) +#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data) +#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data) +#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data) +#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data) +#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data) +#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data) +#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data) +#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data) +#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data) +#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data) +#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data) +#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data) +#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data) +#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data) +#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data) +#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data) +#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data) +#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data) +#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data) +#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data) +#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data) +#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data) +#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data) +#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data) +#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data) +#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data) +#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data) +#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data) +#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data) +#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data) +#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data) +#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data) +#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data) +#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data) +#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data) +#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data) +#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data) +#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data) +#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data) +#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data) +#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data) +#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data) +#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data) +#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data) +#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data) +#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data) +#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data) +#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data) +#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data) +#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data) +#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data) +#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data) +#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data) +#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data) +#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data) +#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data) +#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data) +#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data) +#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data) +#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data) +#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data) +#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data) +#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data) +#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data) +#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data) +#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data) +#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data) +#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data) +#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data) +#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data) +#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data) +#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data) +#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data) +#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data) +#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data) +#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data) +#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data) +#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data) +#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data) +#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data) +#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data) +#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data) +#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data) +#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data) +#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data) +#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data) +#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data) +#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data) +#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data) +#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data) +#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data) +#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data) +#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data) +#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data) +#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data) +#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data) +#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data) +#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data) +#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data) +#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data) +#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data) +#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data) +#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data) +#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data) +#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data) +#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data) +#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data) +#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data) +#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data) +#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data) +#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data) +#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data) +#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data) +#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data) +#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data) +#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data) +#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data) +#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data) +#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data) +#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data) +#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data) +#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data) +#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data) +#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data) +#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data) +#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data) +#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data) +#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data) +#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data) +#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data) +#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data) +#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data) +#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data) +#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data) +#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data) +#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data) +#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data) +#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data) +#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data) +#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data) +#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data) +#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data) +#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data) +#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data) +#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data) +#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data) +#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data) +#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data) +#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data) +#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data) +#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data) +#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data) +#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data) +#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data) +#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data) +#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data) +#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data) +#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data) +#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data) +#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data) +#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data) +#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data) +#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data) +#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data) +#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data) +#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data) +#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data) +#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data) +#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data) +#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data) +#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data) +#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data) +#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data) +#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data) +#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data) +#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data) +#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data) +#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data) +#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data) +#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data) +#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data) +#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data) +#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data) +#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data) +#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data) +#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data) +#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data) +#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data) +#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data) +#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data) +#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data) +#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data) +#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data) +#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data) +#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data) +#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data) +#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data) +#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data) +#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data) +#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data) +#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data) +#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data) +#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data) +#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data) +#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data) +#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data) +#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data) +#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data) +#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data) +#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data) +#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data) +#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data) +#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data) +#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data) +#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data) +#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data) +#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data) +#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data) +#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data) +#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data) +#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data) +#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data) +#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data) +#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data) +#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data) +#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data) +#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data) +#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data) +#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data) +#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data) +#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data) +#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data) +#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data) +#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data) +#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data) +#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data) +#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data) +#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data) +#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data) +#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data) +#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data) +#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data) +#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data) +#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data) +#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data) +#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data) +#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data) +#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data) +#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data) +#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data) +#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data) +#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data) +#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data) +#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data) +#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data) +#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data) + + +#endif // _MREPEAT_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/preprocessor.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/preprocessor.h new file mode 100644 index 0000000..5b996ba --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/preprocessor.h @@ -0,0 +1,55 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _PREPROCESSOR_H_ +#define _PREPROCESSOR_H_ + +#include "tpaste.h" +#include "stringz.h" +#include "mrepeat.h" + + +#endif // _PREPROCESSOR_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/stringz.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/stringz.h new file mode 100644 index 0000000..3528ea0 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/stringz.h @@ -0,0 +1,75 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor stringizing utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _STRINGZ_H_ +#define _STRINGZ_H_ + + +/*! \brief Stringize. + * + * Stringize a preprocessing token, this token being allowed to be \#defined. + * + * May be used only within macros with the token passed as an argument if the token is \#defined. + * + * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN) + * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to + * writing "A0". + */ +#define STRINGZ(x) #x + +/*! \brief Absolute stringize. + * + * Stringize a preprocessing token, this token being allowed to be \#defined. + * + * No restriction of use if the token is \#defined. + * + * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is + * equivalent to writing "A0". + */ +#define ASTRINGZ(x) STRINGZ(x) + + +#endif // _STRINGZ_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/tpaste.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/tpaste.h new file mode 100644 index 0000000..a5d7bee --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/tpaste.h @@ -0,0 +1,95 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor token pasting utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _TPASTE_H_ +#define _TPASTE_H_ + + +/*! \name Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. + * + * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by + * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is + * equivalent to writing U32. + */ +//! @{ +#define TPASTE2( a, b) a##b +#define TPASTE3( a, b, c) a##b##c +#define TPASTE4( a, b, c, d) a##b##c##d +#define TPASTE5( a, b, c, d, e) a##b##c##d##e +#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f +#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g +#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h +#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i +#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j +//! @} + +/*! \name Absolute Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * No restriction of use if the tokens are \#defined. + * + * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined + * as 32 is equivalent to writing U32. + */ +//! @{ +#define ATPASTE2( a, b) TPASTE2( a, b) +#define ATPASTE3( a, b, c) TPASTE3( a, b, c) +#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d) +#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e) +#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f) +#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g) +#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h) +#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i) +#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j) +//! @} + + +#endif // _TPASTE_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/STARTUP_FILES/GCC/crt0.x b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/STARTUP_FILES/GCC/crt0.x new file mode 100644 index 0000000..23b658b --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/STARTUP_FILES/GCC/crt0.x @@ -0,0 +1,121 @@ +/* This file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AVR32UC C runtime startup file. + * + * This file has been built from the Newlib crt0.S. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32UC devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include <avr32/io.h> + + +//! @{ +//! \verbatim + + + // This must be linked @ 0x80000000 if it is to be run upon reset. + .section .reset, "ax", @progbits + + + .global _start + .type _start, @function +_start: + // Jump to the C runtime startup routine. + lda.w pc, _stext + + + // _stext is placed outside the .reset section so that the program entry point + // can be changed without affecting the C runtime startup. + .section .text._stext, "ax", @progbits + + + .global _stext + .type _stext, @function +_stext: + // Set initial stack pointer. + lda.w sp, _estack + + // Set up EVBA so interrupts can be enabled. + lda.w r0, _evba + mtsr AVR32_EVBA, r0 + + // Enable the exception processing. + csrf AVR32_SR_EM_OFFSET + + // Load initialized data having a global lifetime from the data LMA. + lda.w r0, _data + lda.w r1, _edata + cp r0, r1 + brhs idata_load_loop_end + lda.w r2, _data_lma +idata_load_loop: + ld.d r4, r2++ + st.d r0++, r4 + cp r0, r1 + brlo idata_load_loop +idata_load_loop_end: + + // Clear uninitialized data having a global lifetime in the blank static storage section. + lda.w r0, __bss_start + lda.w r1, _end + cp r0, r1 + brhs udata_clear_loop_end + mov r2, 0 + mov r3, 0 +udata_clear_loop: + st.d r0++, r2 + cp r0, r1 + brlo udata_clear_loop +udata_clear_loop_end: + +#ifdef CONFIG_FRAME_POINTER + // Safety: Set the default "return" @ to the exit routine address. + lda.w lr, exit +#endif + + // Start the show. + lda.w pc, main + + +//! \endverbatim +//! @} diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/compiler.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/compiler.h new file mode 100644 index 0000000..885be7f --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/compiler.h @@ -0,0 +1,1145 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Compiler file for AVR32. + * + * This file defines commonly used types and macros. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _COMPILER_H_ +#define _COMPILER_H_ + +#if ((defined __GNUC__) && (defined __AVR32__)) || (defined __ICCAVR32__ || defined __AAVR32__) +# include <avr32/io.h> +#endif +#if (defined __ICCAVR32__) +# include <intrinsics.h> +#endif +#include "preprocessor.h" + +#include "parts.h" + + +//_____ D E C L A R A T I O N S ____________________________________________ + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +#include <stddef.h> +#include <stdlib.h> + + +#if (defined __ICCAVR32__) + +/*! \name Compiler Keywords + * + * Port of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32. + */ +//! @{ +#define __asm__ asm +#define __inline__ inline +#define __volatile__ +//! @} + +#endif + + +/*! \name Usual Types + */ +//! @{ +typedef unsigned char Bool; //!< Boolean. +#ifndef __cplusplus +#if !defined(__bool_true_false_are_defined) +typedef unsigned char bool; //!< Boolean. +#endif +#endif +typedef signed char S8 ; //!< 8-bit signed integer. +typedef unsigned char U8 ; //!< 8-bit unsigned integer. +typedef signed short int S16; //!< 16-bit signed integer. +typedef unsigned short int U16; //!< 16-bit unsigned integer. +typedef signed long int S32; //!< 32-bit signed integer. +typedef unsigned long int U32; //!< 32-bit unsigned integer. +typedef signed long long int S64; //!< 64-bit signed integer. +typedef unsigned long long int U64; //!< 64-bit unsigned integer. +typedef float F32; //!< 32-bit floating-point number. +typedef double F64; //!< 64-bit floating-point number. +//! @} + + +/*! \name Status Types + */ +//! @{ +typedef Bool Status_bool_t; //!< Boolean status. +typedef U8 Status_t; //!< 8-bit-coded status. +//! @} + + +/*! \name Aliasing Aggregate Types + */ +//! @{ + +//! 16-bit union. +typedef union +{ + S16 s16 ; + U16 u16 ; + S8 s8 [2]; + U8 u8 [2]; +} Union16; + +//! 32-bit union. +typedef union +{ + S32 s32 ; + U32 u32 ; + S16 s16[2]; + U16 u16[2]; + S8 s8 [4]; + U8 u8 [4]; +} Union32; + +//! 64-bit union. +typedef union +{ + S64 s64 ; + U64 u64 ; + S32 s32[2]; + U32 u32[2]; + S16 s16[4]; + U16 u16[4]; + S8 s8 [8]; + U8 u8 [8]; +} Union64; + +//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + S64 *s64ptr; + U64 *u64ptr; + S32 *s32ptr; + U32 *u32ptr; + S16 *s16ptr; + U16 *u16ptr; + S8 *s8ptr ; + U8 *u8ptr ; +} UnionPtr; + +//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + volatile S64 *s64ptr; + volatile U64 *u64ptr; + volatile S32 *s32ptr; + volatile U32 *u32ptr; + volatile S16 *s16ptr; + volatile U16 *u16ptr; + volatile S8 *s8ptr ; + volatile U8 *u8ptr ; +} UnionVPtr; + +//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + const S64 *s64ptr; + const U64 *u64ptr; + const S32 *s32ptr; + const U32 *u32ptr; + const S16 *s16ptr; + const U16 *u16ptr; + const S8 *s8ptr ; + const U8 *u8ptr ; +} UnionCPtr; + +//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + const volatile S64 *s64ptr; + const volatile U64 *u64ptr; + const volatile S32 *s32ptr; + const volatile U32 *u32ptr; + const volatile S16 *s16ptr; + const volatile U16 *u16ptr; + const volatile S8 *s8ptr ; + const volatile U8 *u8ptr ; +} UnionCVPtr; + +//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + S64 *s64ptr; + U64 *u64ptr; + S32 *s32ptr; + U32 *u32ptr; + S16 *s16ptr; + U16 *u16ptr; + S8 *s8ptr ; + U8 *u8ptr ; +} StructPtr; + +//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + volatile S64 *s64ptr; + volatile U64 *u64ptr; + volatile S32 *s32ptr; + volatile U32 *u32ptr; + volatile S16 *s16ptr; + volatile U16 *u16ptr; + volatile S8 *s8ptr ; + volatile U8 *u8ptr ; +} StructVPtr; + +//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + const S64 *s64ptr; + const U64 *u64ptr; + const S32 *s32ptr; + const U32 *u32ptr; + const S16 *s16ptr; + const U16 *u16ptr; + const S8 *s8ptr ; + const U8 *u8ptr ; +} StructCPtr; + +//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + const volatile S64 *s64ptr; + const volatile U64 *u64ptr; + const volatile S32 *s32ptr; + const volatile U32 *u32ptr; + const volatile S16 *s16ptr; + const volatile U16 *u16ptr; + const volatile S8 *s8ptr ; + const volatile U8 *u8ptr ; +} StructCVPtr; + +//! @} + +#endif // __AVR32_ABI_COMPILER__ + + +//_____ M A C R O S ________________________________________________________ + +/*! \name Usual Constants + */ +//! @{ +#define DISABLE 0 +#define ENABLE 1 +#define DISABLED 0 +#define ENABLED 1 +#define OFF 0 +#define ON 1 +#define FALSE 0 +#define TRUE 1 +#ifndef __cplusplus +#if !defined(__bool_true_false_are_defined) +#define false FALSE +#define true TRUE +#endif +#endif +#define KO 0 +#define OK 1 +#define PASS 0 +#define FAIL 1 +#define LOW 0 +#define HIGH 1 +#define CLR 0 +#define SET 1 +//! @} + + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +/*! \name Bit-Field Handling + */ +//! @{ + +/*! \brief Reads the bits of a value specified by a given bit-mask. + * + * \param value Value to read bits from. + * \param mask Bit-mask indicating bits to read. + * + * \return Read bits. + */ +#define Rd_bits( value, mask) ((value) & (mask)) + +/*! \brief Writes the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue to write bits to. + * \param mask Bit-mask indicating bits to write. + * \param bits Bits to write. + * + * \return Resulting value with written bits. + */ +#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\ + ((bits ) & (mask))) + +/*! \brief Tests the bits of a value specified by a given bit-mask. + * + * \param value Value of which to test bits. + * \param mask Bit-mask indicating bits to test. + * + * \return \c 1 if at least one of the tested bits is set, else \c 0. + */ +#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0) + +/*! \brief Clears the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to clear bits. + * \param mask Bit-mask indicating bits to clear. + * + * \return Resulting value with cleared bits. + */ +#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask)) + +/*! \brief Sets the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to set bits. + * \param mask Bit-mask indicating bits to set. + * + * \return Resulting value with set bits. + */ +#define Set_bits(lvalue, mask) ((lvalue) |= (mask)) + +/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to toggle bits. + * \param mask Bit-mask indicating bits to toggle. + * + * \return Resulting value with toggled bits. + */ +#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask)) + +/*! \brief Reads the bit-field of a value specified by a given bit-mask. + * + * \param value Value to read a bit-field from. + * \param mask Bit-mask indicating the bit-field to read. + * + * \return Read bit-field. + */ +#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask)) + +/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue to write a bit-field to. + * \param mask Bit-mask indicating the bit-field to write. + * \param bitfield Bit-field to write. + * + * \return Resulting value with written bit-field. + */ +#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask))) + +//! @} + + +/*! \brief This macro is used to test fatal errors. + * + * The macro tests if the expression is FALSE. If it is, a fatal error is + * detected and the application hangs up. + * + * \param expr Expression to evaluate and supposed to be nonzero. + */ +#ifdef _ASSERT_ENABLE_ + #define Assert(expr) \ + {\ + if (!(expr)) while (TRUE);\ + } +#else + #define Assert(expr) +#endif + + +/*! \name Zero-Bit Counting + * + * Under AVR32-GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + */ +//! @{ + +/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) + #define clz(u) __builtin_clz(u) +#elif (defined __ICCAVR32__) + #define clz(u) __count_leading_zeros(u) +#endif + +/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) + #define ctz(u) __builtin_ctz(u) +#elif (defined __ICCAVR32__) + #define ctz(u) __count_trailing_zeros(u) +#endif + +//! @} + + +/*! \name Bit Reversing + */ +//! @{ + +/*! \brief Reverses the bits of \a u8. + * + * \param u8 U8 of which to reverse the bits. + * + * \return Value resulting from \a u8 with reversed bits. + */ +#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24)) + +/*! \brief Reverses the bits of \a u16. + * + * \param u16 U16 of which to reverse the bits. + * + * \return Value resulting from \a u16 with reversed bits. + */ +#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16)) + +/*! \brief Reverses the bits of \a u32. + * + * \param u32 U32 of which to reverse the bits. + * + * \return Value resulting from \a u32 with reversed bits. + */ +#if (defined __GNUC__) + #define bit_reverse32(u32) \ + (\ + {\ + unsigned int __value = (U32)(u32);\ + __asm__ ("brev\t%0" : "+r" (__value) : : "cc");\ + (U32)__value;\ + }\ + ) +#elif (defined __ICCAVR32__) + #define bit_reverse32(u32) ((U32)__bit_reverse((U32)(u32))) +#endif + +/*! \brief Reverses the bits of \a u64. + * + * \param u64 U64 of which to reverse the bits. + * + * \return Value resulting from \a u64 with reversed bits. + */ +#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\ + ((U64)bit_reverse32((U64)(u64)) << 32))) + +//! @} + + +/*! \name Alignment + */ +//! @{ + +/*! \brief Tests alignment of the number \a val with the \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0. + */ +#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) ) + +/*! \brief Gets alignment of the number \a val with respect to the \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Alignment of the number \a val with respect to the \a n boundary. + */ +#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) ) + +/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary. + * + * \param lval Input/output lvalue. + * \param n Boundary. + * \param alg Alignment. + * + * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary. + */ +#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) ) + +/*! \brief Aligns the number \a val with the upper \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Value resulting from the number \a val aligned with the upper \a n boundary. + */ +#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1)) + +/*! \brief Aligns the number \a val with the lower \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Value resulting from the number \a val aligned with the lower \a n boundary. + */ +#define Align_down(val, n ) ( (val) & ~((n) - 1)) + +//! @} + + +/*! \name Mathematics + * + * The same considerations as for clz and ctz apply here but AVR32-GCC does not + * provide built-in functions to access the assembly instructions abs, min and + * max and it does not produce them by itself in most cases, so two sets of + * macros are defined here: + * - Abs, Min and Max to apply to constant expressions (values known at + * compile time); + * - abs, min and max to apply to non-constant expressions (values unknown at + * compile time). + */ +//! @{ + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values known at compile time. + */ +#define Abs(a) (((a) < 0 ) ? -(a) : (a)) + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Min(a, b) (((a) < (b)) ? (a) : (b)) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Max(a, b) (((a) > (b)) ? (a) : (b)) + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) + #define abs(a) \ + (\ + {\ + int __value = (a);\ + __asm__ ("abs\t%0" : "+r" (__value) : : "cc");\ + __value;\ + }\ + ) +#elif (defined __ICCAVR32__) + #define abs(a) Abs(a) +#endif + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) + #define min(a, b) \ + (\ + {\ + int __value, __arg_a = (a), __arg_b = (b);\ + __asm__ ("min\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\ + __value;\ + }\ + ) +#elif (defined __ICCAVR32__) + #define min(a, b) __min(a, b) +#endif + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) + #define max(a, b) \ + (\ + {\ + int __value, __arg_a = (a), __arg_b = (b);\ + __asm__ ("max\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\ + __value;\ + }\ + ) +#elif (defined __ICCAVR32__) + #define max(a, b) __max(a, b) +#endif + +//! @} + + +/*! \brief Calls the routine at address \a addr. + * + * It generates a long call opcode. + * + * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if + * it is invoked from the CPU supervisor mode. + * + * \param addr Address of the routine to call. + * + * \note It may be used as a long jump opcode in some special cases. + */ +#define Long_call(addr) ((*(void (*)(void))(addr))()) + +/*! \brief Resets the CPU by software. + * + * \warning It shall not be called from the CPU application mode. + */ +#if (defined __GNUC__) + #define Reset_CPU() \ + (\ + {\ + __asm__ __volatile__ (\ + "lddpc r9, 3f\n\t"\ + "mfsr r8, %[SR]\n\t"\ + "bfextu r8, r8, %[SR_M_OFFSET], %[SR_M_SIZE]\n\t"\ + "cp.w r8, 0b001\n\t"\ + "breq 0f\n\t"\ + "sub r8, pc, $ - 1f\n\t"\ + "pushm r8-r9\n\t"\ + "rete\n"\ + "0:\n\t"\ + "mtsr %[SR], r9\n"\ + "1:\n\t"\ + "mov r0, 0\n\t"\ + "mov r1, 0\n\t"\ + "mov r2, 0\n\t"\ + "mov r3, 0\n\t"\ + "mov r4, 0\n\t"\ + "mov r5, 0\n\t"\ + "mov r6, 0\n\t"\ + "mov r7, 0\n\t"\ + "mov r8, 0\n\t"\ + "mov r9, 0\n\t"\ + "mov r10, 0\n\t"\ + "mov r11, 0\n\t"\ + "mov r12, 0\n\t"\ + "mov sp, 0\n\t"\ + "stdsp sp[0], sp\n\t"\ + "ldmts sp, sp\n\t"\ + "mov lr, 0\n\t"\ + "lddpc pc, 2f\n\t"\ + ".balign 4\n"\ + "2:\n\t"\ + ".word _start\n"\ + "3:\n\t"\ + ".word %[RESET_SR]"\ + :\ + : [SR] "i" (AVR32_SR),\ + [SR_M_OFFSET] "i" (AVR32_SR_M_OFFSET),\ + [SR_M_SIZE] "i" (AVR32_SR_M_SIZE),\ + [RESET_SR] "i" (AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))\ + );\ + }\ + ) +#elif (defined __ICCAVR32__) + #define Reset_CPU() \ + {\ + extern void *volatile __program_start;\ + __asm__ __volatile__ (\ + "mov r7, LWRD(__program_start)\n\t"\ + "orh r7, HWRD(__program_start)\n\t"\ + "mov r9, LWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))")\n\t"\ + "orh r9, HWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))")\n\t"\ + "mfsr r8, "ASTRINGZ(AVR32_SR)"\n\t"\ + "bfextu r8, r8, "ASTRINGZ(AVR32_SR_M_OFFSET)", "ASTRINGZ(AVR32_SR_M_SIZE)"\n\t"\ + "cp.w r8, 001b\n\t"\ + "breq $ + 10\n\t"\ + "sub r8, pc, -12\n\t"\ + "pushm r8-r9\n\t"\ + "rete\n\t"\ + "mtsr "ASTRINGZ(AVR32_SR)", r9\n\t"\ + "mov r0, 0\n\t"\ + "mov r1, 0\n\t"\ + "mov r2, 0\n\t"\ + "mov r3, 0\n\t"\ + "mov r4, 0\n\t"\ + "mov r5, 0\n\t"\ + "mov r6, 0\n\t"\ + "st.w r0[4], r7\n\t"\ + "mov r7, 0\n\t"\ + "mov r8, 0\n\t"\ + "mov r9, 0\n\t"\ + "mov r10, 0\n\t"\ + "mov r11, 0\n\t"\ + "mov r12, 0\n\t"\ + "mov sp, 0\n\t"\ + "stdsp sp[0], sp\n\t"\ + "ldmts sp, sp\n\t"\ + "mov lr, 0\n\t"\ + "ld.w pc, lr[4]"\ + );\ + __program_start;\ + } +#endif + + +/*! \name System Register Access + */ +//! @{ + +/*! \brief Gets the value of the \a sysreg system register. + * + * \param sysreg Address of the system register of which to get the value. + * + * \return Value of the \a sysreg system register. + */ +#if (defined __GNUC__) + #define Get_system_register(sysreg) __builtin_mfsr(sysreg) +#elif (defined __ICCAVR32__) + #define Get_system_register(sysreg) __get_system_register(sysreg) +#endif + +/*! \brief Sets the value of the \a sysreg system register to \a value. + * + * \param sysreg Address of the system register of which to set the value. + * \param value Value to set the \a sysreg system register to. + */ +#if (defined __GNUC__) + #define Set_system_register(sysreg, value) __builtin_mtsr(sysreg, value) +#elif (defined __ICCAVR32__) + #define Set_system_register(sysreg, value) __set_system_register(sysreg, value) +#endif + +//! @} + + +/*! \name CPU Status Register Access + */ +//! @{ + +/*! \brief Tells whether exceptions are globally enabled. + * + * \return \c 1 if exceptions are globally enabled, else \c 0. + */ +#define Is_global_exception_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_EM_MASK)) + +/*! \brief Disables exceptions globally. + */ +#if (defined __GNUC__) + #define Disable_global_exception() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));}) +#elif (defined __ICCAVR32__) + #define Disable_global_exception() (__set_status_flag(AVR32_SR_EM_OFFSET)) +#endif + +/*! \brief Enables exceptions globally. + */ +#if (defined __GNUC__) + #define Enable_global_exception() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));}) +#elif (defined __ICCAVR32__) + #define Enable_global_exception() (__clear_status_flag(AVR32_SR_EM_OFFSET)) +#endif + +/*! \brief Tells whether interrupts are globally enabled. + * + * \return \c 1 if interrupts are globally enabled, else \c 0. + */ +#define Is_global_interrupt_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_GM_MASK)) + +/*! \brief Disables interrupts globally. + */ +#if (defined __GNUC__) + #define Disable_global_interrupt() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_GM_OFFSET));}) +#elif (defined __ICCAVR32__) + #define Disable_global_interrupt() (__disable_interrupt()) +#endif + +/*! \brief Enables interrupts globally. + */ +#if (defined __GNUC__) + #define Enable_global_interrupt() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_GM_OFFSET));}) +#elif (defined __ICCAVR32__) + #define Enable_global_interrupt() (__enable_interrupt()) +#endif + +/*! \brief Tells whether interrupt level \a int_level is enabled. + * + * \param int_level Interrupt level (0 to 3). + * + * \return \c 1 if interrupt level \a int_level is enabled, else \c 0. + */ +#define Is_interrupt_level_enabled(int_level) (!Tst_bits(Get_system_register(AVR32_SR), TPASTE3(AVR32_SR_I, int_level, M_MASK))) + +/*! \brief Disables interrupt level \a int_level. + * + * \param int_level Interrupt level to disable (0 to 3). + */ +#if (defined __GNUC__) + #define Disable_interrupt_level(int_level) ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (TPASTE3(AVR32_SR_I, int_level, M_OFFSET)));}) +#elif (defined __ICCAVR32__) + #define Disable_interrupt_level(int_level) (__set_status_flag(TPASTE3(AVR32_SR_I, int_level, M_OFFSET))) +#endif + +/*! \brief Enables interrupt level \a int_level. + * + * \param int_level Interrupt level to enable (0 to 3). + */ +#if (defined __GNUC__) + #define Enable_interrupt_level(int_level) ({__asm__ __volatile__ ("csrf\t%0" : : "i" (TPASTE3(AVR32_SR_I, int_level, M_OFFSET)));}) +#elif (defined __ICCAVR32__) + #define Enable_interrupt_level(int_level) (__clear_status_flag(TPASTE3(AVR32_SR_I, int_level, M_OFFSET))) +#endif + +/*! \brief Protects subsequent code from interrupts. + */ +#define AVR32_ENTER_CRITICAL_REGION( ) \ + { \ + Bool global_interrupt_enabled = Is_global_interrupt_enabled(); \ + Disable_global_interrupt(); // Disable the appropriate interrupts. + +/*! \brief This macro must always be used in conjunction with AVR32_ENTER_CRITICAL_REGION + * so that interrupts are enabled again. + */ +#define AVR32_LEAVE_CRITICAL_REGION( ) \ + if (global_interrupt_enabled) Enable_global_interrupt(); \ + } + +//! @} + + +/*! \name Debug Register Access + */ +//! @{ + +/*! \brief Gets the value of the \a dbgreg debug register. + * + * \param dbgreg Address of the debug register of which to get the value. + * + * \return Value of the \a dbgreg debug register. + */ +#if (defined __GNUC__) + #define Get_debug_register(dbgreg) __builtin_mfdr(dbgreg) +#elif (defined __ICCAVR32__) + #define Get_debug_register(dbgreg) __get_debug_register(dbgreg) +#endif + +/*! \brief Sets the value of the \a dbgreg debug register to \a value. + * + * \param dbgreg Address of the debug register of which to set the value. + * \param value Value to set the \a dbgreg debug register to. + */ +#if (defined __GNUC__) + #define Set_debug_register(dbgreg, value) __builtin_mtdr(dbgreg, value) +#elif (defined __ICCAVR32__) + #define Set_debug_register(dbgreg, value) __set_debug_register(dbgreg, value) +#endif + +//! @} + +#endif // __AVR32_ABI_COMPILER__ + + +//! Boolean evaluating MCU little endianism. +#if ((defined __GNUC__) && (defined __AVR32__)) || ((defined __ICCAVR32__) || (defined __AAVR32__)) + #define LITTLE_ENDIAN_MCU FALSE +#else + #error If you are here, you should check what is exactly the processor you are using... + #define LITTLE_ENDIAN_MCU FALSE +#endif + +// Check that MCU endianism is correctly defined. +#ifndef LITTLE_ENDIAN_MCU + #error YOU MUST define the MCU endianism with LITTLE_ENDIAN_MCU: either FALSE or TRUE +#endif + +//! Boolean evaluating MCU big endianism. +#define BIG_ENDIAN_MCU (!LITTLE_ENDIAN_MCU) + + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +/*! \name MCU Endianism Handling + */ +//! @{ + +#if (LITTLE_ENDIAN_MCU==TRUE) + #define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16. + #define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16. + + #define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32. + #define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32. + #define LSB0W(u32) (((U8 *)&(u32))[0]) //!< Least significant byte of 1st rank of \a u32. + #define LSB1W(u32) (((U8 *)&(u32))[1]) //!< Least significant byte of 2nd rank of \a u32. + #define LSB2W(u32) (((U8 *)&(u32))[2]) //!< Least significant byte of 3rd rank of \a u32. + #define LSB3W(u32) (((U8 *)&(u32))[3]) //!< Least significant byte of 4th rank of \a u32. + #define MSB3W(u32) LSB0W(u32) //!< Most significant byte of 4th rank of \a u32. + #define MSB2W(u32) LSB1W(u32) //!< Most significant byte of 3rd rank of \a u32. + #define MSB1W(u32) LSB2W(u32) //!< Most significant byte of 2nd rank of \a u32. + #define MSB0W(u32) LSB3W(u32) //!< Most significant byte of 1st rank of \a u32. + + #define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64. + #define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64. + #define LSH0(u64) (((U16 *)&(u64))[0]) //!< Least significant half-word of 1st rank of \a u64. + #define LSH1(u64) (((U16 *)&(u64))[1]) //!< Least significant half-word of 2nd rank of \a u64. + #define LSH2(u64) (((U16 *)&(u64))[2]) //!< Least significant half-word of 3rd rank of \a u64. + #define LSH3(u64) (((U16 *)&(u64))[3]) //!< Least significant half-word of 4th rank of \a u64. + #define MSH3(u64) LSH0(u64) //!< Most significant half-word of 4th rank of \a u64. + #define MSH2(u64) LSH1(u64) //!< Most significant half-word of 3rd rank of \a u64. + #define MSH1(u64) LSH2(u64) //!< Most significant half-word of 2nd rank of \a u64. + #define MSH0(u64) LSH3(u64) //!< Most significant half-word of 1st rank of \a u64. + #define LSB0D(u64) (((U8 *)&(u64))[0]) //!< Least significant byte of 1st rank of \a u64. + #define LSB1D(u64) (((U8 *)&(u64))[1]) //!< Least significant byte of 2nd rank of \a u64. + #define LSB2D(u64) (((U8 *)&(u64))[2]) //!< Least significant byte of 3rd rank of \a u64. + #define LSB3D(u64) (((U8 *)&(u64))[3]) //!< Least significant byte of 4th rank of \a u64. + #define LSB4D(u64) (((U8 *)&(u64))[4]) //!< Least significant byte of 5th rank of \a u64. + #define LSB5D(u64) (((U8 *)&(u64))[5]) //!< Least significant byte of 6th rank of \a u64. + #define LSB6D(u64) (((U8 *)&(u64))[6]) //!< Least significant byte of 7th rank of \a u64. + #define LSB7D(u64) (((U8 *)&(u64))[7]) //!< Least significant byte of 8th rank of \a u64. + #define MSB7D(u64) LSB0D(u64) //!< Most significant byte of 8th rank of \a u64. + #define MSB6D(u64) LSB1D(u64) //!< Most significant byte of 7th rank of \a u64. + #define MSB5D(u64) LSB2D(u64) //!< Most significant byte of 6th rank of \a u64. + #define MSB4D(u64) LSB3D(u64) //!< Most significant byte of 5th rank of \a u64. + #define MSB3D(u64) LSB4D(u64) //!< Most significant byte of 4th rank of \a u64. + #define MSB2D(u64) LSB5D(u64) //!< Most significant byte of 3rd rank of \a u64. + #define MSB1D(u64) LSB6D(u64) //!< Most significant byte of 2nd rank of \a u64. + #define MSB0D(u64) LSB7D(u64) //!< Most significant byte of 1st rank of \a u64. + +#elif (BIG_ENDIAN_MCU==TRUE) + #define MSB(u16) (((U8 *)&(u16))[0]) //!< Most significant byte of \a u16. + #define LSB(u16) (((U8 *)&(u16))[1]) //!< Least significant byte of \a u16. + + #define MSH(u32) (((U16 *)&(u32))[0]) //!< Most significant half-word of \a u32. + #define LSH(u32) (((U16 *)&(u32))[1]) //!< Least significant half-word of \a u32. + #define MSB0W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 1st rank of \a u32. + #define MSB1W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 2nd rank of \a u32. + #define MSB2W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 3rd rank of \a u32. + #define MSB3W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 4th rank of \a u32. + #define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32. + #define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32. + #define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32. + #define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32. + + #define MSW(u64) (((U32 *)&(u64))[0]) //!< Most significant word of \a u64. + #define LSW(u64) (((U32 *)&(u64))[1]) //!< Least significant word of \a u64. + #define MSH0(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 1st rank of \a u64. + #define MSH1(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 2nd rank of \a u64. + #define MSH2(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 3rd rank of \a u64. + #define MSH3(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 4th rank of \a u64. + #define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64. + #define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64. + #define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64. + #define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64. + #define MSB0D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 1st rank of \a u64. + #define MSB1D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 2nd rank of \a u64. + #define MSB2D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 3rd rank of \a u64. + #define MSB3D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 4th rank of \a u64. + #define MSB4D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 5th rank of \a u64. + #define MSB5D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 6th rank of \a u64. + #define MSB6D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 7th rank of \a u64. + #define MSB7D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 8th rank of \a u64. + #define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64. + #define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64. + #define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64. + #define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64. + #define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64. + #define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64. + #define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64. + #define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64. + +#else + #error Unknown endianism. +#endif + +//! @} + + +/*! \name Endianism Conversion + * + * The same considerations as for clz and ctz apply here but AVR32-GCC's + * __builtin_bswap_16 and __builtin_bswap_32 do not behave like macros when + * applied to constant expressions, so two sets of macros are defined here: + * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known + * at compile time); + * - swap16, swap32 and swap64 to apply to non-constant expressions (values + * unknown at compile time). + */ +//! @{ + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\ + ((U16)(u16) << 8))) + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\ + ((U32)Swap16((U32)(u32)) << 16))) + +/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). + * + * \param u64 U64 of which to toggle the endianism. + * + * \return Value resulting from \a u64 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\ + ((U64)Swap32((U64)(u64)) << 32))) + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) + #define swap16(u16) ((U16)__builtin_bswap_16((U16)(u16))) +#elif (defined __ICCAVR32__) + #define swap16(u16) ((U16)__swap_bytes_in_halfwords((U16)(u16))) +#endif + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) + #define swap32(u32) ((U32)__builtin_bswap_32((U32)(u32))) +#elif (defined __ICCAVR32__) + #define swap32(u32) ((U32)__swap_bytes((U32)(u32))) +#endif + +/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). + * + * \param u64 U64 of which to toggle the endianism. + * + * \return Value resulting from \a u64 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\ + ((U64)swap32((U64)(u64)) << 32))) + +//! @} + + +/*! \name Target Abstraction + */ +//! @{ + +#define _GLOBEXT_ extern //!< extern storage-class specifier. +#define _CONST_TYPE_ const //!< const type qualifier. +#define _MEM_TYPE_SLOW_ //!< Slow memory type. +#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type. +#define _MEM_TYPE_FAST_ //!< Fast memory type. + +typedef U8 Byte; //!< 8-bit unsigned integer. + +#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM. +#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM. +#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM. +#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM. + +#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32. +#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32. +#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32. +#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32. +#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32. +#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32. +#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32. +#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32. + +//! @} + +#endif // __AVR32_ABI_COMPILER__ + + +#endif // _COMPILER_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/conf_isp.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/conf_isp.h new file mode 100644 index 0000000..ca516ee --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/conf_isp.h @@ -0,0 +1,136 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ****************************************************************** + * + * \brief ISP configuration file. + * + * This file contains the possible external configuration of the ISP. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USB module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ***************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _CONF_ISP_H_ +#define _CONF_ISP_H_ + +#include <avr32/io.h> +#include "compiler.h" + + +//_____ D E F I N I T I O N S ______________________________________________ + +#define PRODUCT_MANUFACTURER_ID 0x58 +#define PRODUCT_FAMILY_ID 0x20 + +#define ISP_VERSION 0x10 +#define ISP_ID0 0x00 +#define ISP_ID1 0x00 + +#define ISP_CFG1 (*(volatile U32 *)ISP_CFG1_ADDRESS) +#define ISP_CFG1_ADDRESS (AVR32_FLASHC_USER_PAGE_ADDRESS + ISP_CFG1_OFFSET) +#define ISP_CFG1_OFFSET 0x000001FC +#define ISP_CFG1_SIZE 4 + +#define ISP_CFG1_BOOT_KEY1 16 +#define ISP_CFG1_BOOT_KEY1_MASK 0xFFFF0000 +#define ISP_CFG1_BOOT_KEY1_OFFSET 16 +#define ISP_CFG1_BOOT_KEY1_SIZE 16 +#define ISP_CFG1_BOOT_KEY1_VALUE 0xE11E + +#define ISP_CFG1_FORCE 9 +#define ISP_CFG1_FORCE_MASK 0x00000200 +#define ISP_CFG1_FORCE_OFFSET 9 +#define ISP_CFG1_FORCE_SIZE 1 + +#define ISP_CFG1_IO_COND_EN 8 +#define ISP_CFG1_IO_COND_EN_MASK 0x00000100 +#define ISP_CFG1_IO_COND_EN_OFFSET 8 +#define ISP_CFG1_IO_COND_EN_SIZE 1 + +#define ISP_CFG1_CRC8 0 +#define ISP_CFG1_CRC8_MASK 0x000000FF +#define ISP_CFG1_CRC8_OFFSET 0 +#define ISP_CFG1_CRC8_SIZE 8 +#define ISP_CFG1_CRC8_POLYNOMIAL 0x107 + +#define ISP_CFG2 (*(volatile U32 *)ISP_CFG2_ADDRESS) +#define ISP_CFG2_ADDRESS (AVR32_FLASHC_USER_PAGE_ADDRESS + ISP_CFG2_OFFSET) +#define ISP_CFG2_OFFSET 0x000001F8 +#define ISP_CFG2_SIZE 4 + +#define ISP_CFG2_BOOT_KEY 17 +#define ISP_CFG2_BOOT_KEY_MASK 0xFFFE0000 +#define ISP_CFG2_BOOT_KEY_OFFSET 17 +#define ISP_CFG2_BOOT_KEY_SIZE 15 +#define ISP_CFG2_BOOT_KEY_VALUE 0x494F + +#define ISP_CFG2_IO_COND_LEVEL 16 +#define ISP_CFG2_IO_COND_LEVEL_MASK 0x00010000 +#define ISP_CFG2_IO_COND_LEVEL_OFFSET 16 +#define ISP_CFG2_IO_COND_LEVEL_SIZE 1 + +#define ISP_CFG2_IO_COND_PIN 8 +#define ISP_CFG2_IO_COND_PIN_MASK 0x0000FF00 +#define ISP_CFG2_IO_COND_PIN_OFFSET 8 +#define ISP_CFG2_IO_COND_PIN_SIZE 8 + +#define ISP_CFG2_CRC8 0 +#define ISP_CFG2_CRC8_MASK 0x000000FF +#define ISP_CFG2_CRC8_OFFSET 0 +#define ISP_CFG2_CRC8_SIZE 8 +#define ISP_CFG2_CRC8_POLYNOMIAL 0x107 + +#define ISP_KEY (*(volatile U32 *)ISP_KEY_ADDRESS) +#define ISP_KEY_ADDRESS (AVR32_SRAM_ADDRESS + ISP_KEY_OFFSET) +#define ISP_KEY_OFFSET 0x00000000 +#define ISP_KEY_SIZE 4 +#define ISP_KEY_VALUE ('I' << 24 | 'S' << 16 | 'P' << 8 | 'K') + +#ifndef ISP_OSC + #define ISP_OSC 0 +#endif + +#define DFU_FRAME_LENGTH 2048 + +#define PROGRAM_START_ADDRESS (AVR32_FLASH_ADDRESS + PROGRAM_START_OFFSET) +#define PROGRAM_START_OFFSET 0x00002000 + + +#endif // _CONF_ISP_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/parts.h b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/parts.h new file mode 100644 index 0000000..6637b2f --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/UTILS/parts.h @@ -0,0 +1,203 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Arch file for AVR32. + * + * This file defines common AVR32 UC3 series. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _ARCH_H_ +#define _ARCH_H_ + +// UC3 A Series +#define UC3A0 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3A0128__) || \ + defined (__AVR32_UC3A0256__) || \ + defined (__AVR32_UC3A0512__) || \ + defined (__AVR32_UC3A0512ES__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3A0128__) || \ + defined (__AT32UC3A0256__) || \ + defined (__AT32UC3A0512__) || \ + defined (__AT32UC3A0512ES__))) + +#define UC3A1 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3A1128__) || \ + defined (__AVR32_UC3A1256__) || \ + defined (__AVR32_UC3A1512__) || \ + defined (__AVR32_UC3A1512ES__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3A1128__) || \ + defined (__AT32UC3A1256__) || \ + defined (__AT32UC3A1512__) || \ + defined (__AT32UC3A1512ES__))) + +#define UC3A3 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3A364__) || \ + defined (__AVR32_UC3A364S__) || \ + defined (__AVR32_UC3A3128__) || \ + defined (__AVR32_UC3A3128S__) || \ + defined (__AVR32_UC3A3256__) || \ + defined (__AVR32_UC3A3256S__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3A364__) || \ + defined (__AT32UC3A364S__) || \ + defined (__AT32UC3A3128__) || \ + defined (__AT32UC3A3128S__) || \ + defined (__AT32UC3A3256__) || \ + defined (__AT32UC3A3256S__))) + +#define UC3A (UC3A0 || UC3A1 || UC3A3) + +// UC3 B Series +#define UC3B0 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3B064__) || \ + defined (__AVR32_UC3B0128__) || \ + defined (__AVR32_UC3B0256__) || \ + defined (__AVR32_UC3B0256ES__) || \ + defined (__AVR32_UC3B0512__) || \ + defined (__AVR32_UC3B0512REVC_))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3B064__) || \ + defined (__AT32UC3B0128__) || \ + defined (__AT32UC3B0256__) || \ + defined (__AT32UC3B0256ES__) || \ + defined (__AT32UC3B0512__) || \ + defined (__AT32UC3B0512REVC__))) + +#define UC3B1 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3B164__) || \ + defined (__AVR32_UC3B1128__) || \ + defined (__AVR32_UC3B1256__) || \ + defined (__AVR32_UC3B1256ES__) || \ + defined (__AVR32_UC3B1512__) || \ + defined (__AVR32_UC3B1512ES__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3B164__) || \ + defined (__AT32UC3B1128__) || \ + defined (__AT32UC3B1256__) || \ + defined (__AT32UC3B1256ES__) || \ + defined (__AT32UC3B1512__) || \ + defined (__AT32UC3B1512REVC__))) + +#define UC3B (UC3B0 || UC3B1 ) + +// UC3 C Series +#define UC3C0 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3C064C__) || \ + defined (__AVR32_UC3C0128C__) || \ + defined (__AVR32_UC3C0256C__) || \ + defined (__AVR32_UC3C0512CREVC__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3C064C__) || \ + defined (__AT32UC3C0128C__) || \ + defined (__AT32UC3C0256C__) || \ + defined (__AT32UC3C0512C__))) + +#define UC3C1 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3C164C__) || \ + defined (__AVR32_UC3C1128C__) || \ + defined (__AVR32_UC3C1256C__) || \ + defined (__AVR32_UC3C1512CREVC__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3C164C__) || \ + defined (__AT32UC3C1128C__) || \ + defined (__AT32UC3C1256C__) || \ + defined (__AT32UC3C1512C__))) + +#define UC3C2 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3C264C__) || \ + defined (__AVR32_UC3C2128C__) || \ + defined (__AVR32_UC3C2256C__) || \ + defined (__AVR32_UC3C2512CREVC__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3C264C__) || \ + defined (__AT32UC3C2128C__) || \ + defined (__AT32UC3C2256C__) || \ + defined (__AT32UC3C2512C__))) + +#define UC3C (UC3C0 || UC3C1 || UC3C2) + +// UC3 L Device series +#define UC3L0 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3L016__) || \ + defined (__AVR32_UC3L032__) || \ + defined (__AVR32_UC3L064__) || \ + defined (__AVR32_UC3L064REVB__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3L016__) || \ + defined (__AT32UC3L032__) || \ + defined (__AT32UC3L064__) || \ + defined (__AT32UC3L064REVB__))) + +#define UC3L1 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3L116__) || \ + defined (__AVR32_UC3L132__) || \ + defined (__AVR32_UC3L164__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3L116__) || \ + defined (__AT32UC3L132__) || \ + defined (__AT32UC3L164__))) + +#define UC3L2 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3L216__) || \ + defined (__AVR32_UC3L232__) || \ + defined (__AVR32_UC3L264__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3L216__) || \ + defined (__AT32UC3L232__) || \ + defined (__AT32UC3L264__))) + +#define UC3L3 ( defined (__GNUC__) && \ + ( defined (__AVR32_UC3L316__) || \ + defined (__AVR32_UC3L332__) || \ + defined (__AVR32_UC3L364__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3L316__) || \ + defined (__AT32UC3L332__) || \ + defined (__AT32UC3L364__))) + +#define UC3L (UC3L0 || UC3L1 || UC3L2 || UC3L3) + +#endif // _ARCH_H_ diff --git a/firmwares/wifishield/wifi_dnld/src/clocks.c b/firmwares/wifishield/wifi_dnld/src/clocks.c new file mode 100644 index 0000000..cdd07fa --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/clocks.c @@ -0,0 +1,101 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include <avr32/io.h> +#include "board.h" +#include "clocks.h" +#include "pm.h" +#include "flashc.h" +#include "gpio.h" + +/** + * Initializes the MCU system clocks. + */ +void +init_sys_clocks(void) +{ + /* switch to OSC0 to speed up the booting */ + pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP); + +#ifndef USE_PLL + return; +#endif + + /* For audio, ee have to use OSC1 on to generate the correct clockrate + * for the SSC + */ +#if OSC == 1 + /* start oscillator1 */ + pm_enable_osc1_crystal(&AVR32_PM, FOSC1); + pm_enable_clk1(&AVR32_PM, OSC1_STARTUP); +#endif + + /* configure pll multipliers */ + pm_pll_setup(&AVR32_PM, + 0, /* pll */ + PLL_MUL, /* mul */ + 1, /* div */ + OSC, /* osc */ + 16); /* lockcount */ + + /* set PLL operating range and divider (fpll = fvco/2) + * this gives PLL output = 66 MHz (62.0928 MHz for EVK1105/OSC1) + */ + pm_pll_set_option(&AVR32_PM, + 0, /* pll */ + 1, /* pll_freq */ + 1, /* pll_div2 */ + 0); /* pll_wbwdisable. */ + + + /* start PLL0 and wait for the lock */ + pm_pll_enable(&AVR32_PM, 0); + pm_wait_for_pll0_locked(&AVR32_PM); + + /* Set all peripheral clocks torun at master clock rate */ + pm_cksel(&AVR32_PM, + 0, /* pbadiv */ + 0, /* pbasel */ + 0, /* pbbdiv */ + 0, /* pbbsel */ + 0, /* hsbdiv */ + 0); /* hsbsel */ + + /* Set one waitstate for the flash */ + flashc_set_wait_state(1); + + /* Switch to PLL0 as the master clock */ + pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0); + +#if OSC == 1 + pm_configure_usb_clock(); +#endif +} diff --git a/firmwares/wifishield/wifi_dnld/src/clocks.h b/firmwares/wifishield/wifi_dnld/src/clocks.h new file mode 100644 index 0000000..cceda29 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/clocks.h @@ -0,0 +1,78 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef CLOCKS_H +#define CLOCKS_H + +#include "board.h" + + +#if BOARD == EVK1100 +# define USE_PLL +# define OSC 0 +# define PLL_MUL 10 +#elif BOARD == EVK1101 +# define USE_PLL +# define OSC 0 +# define PLL_MUL 9 +#elif BOARD == EVK1104 +# define USE_PLL +# define OSC 0 +# define PLL_MUL 9 /* for some reason we cant use 66 MHz */ +#elif BOARD == EVK1105 +# define USE_PLL +# define OSC 1 +# define PLL_MUL 10 +#elif BOARD == ARDUINO +# define USE_PLL +# define OSC 0 +# define PLL_MUL 8 +#endif + +#if OSC == 0 +# define FOSC FOSC0 /* 12 MHz */ +#else +# define FOSC FOSC1 /* 11.2896 MHz */ +#endif + +#ifdef USE_PLL +# define FMCK_HZ ((FOSC * (PLL_MUL + 1)) / 2) +#else +# define FMCK_HZ FOSC +#endif + +#define FCPU_HZ FMCK_HZ +#define FHSB_HZ FCPU_HZ +#define FPBB_HZ FMCK_HZ +#define FPBA_HZ FMCK_HZ + +void init_sys_clocks(void); + +#endif diff --git a/firmwares/wifishield/wifi_dnld/src/flash_fw.c b/firmwares/wifishield/wifi_dnld/src/flash_fw.c new file mode 100644 index 0000000..75d35f6 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/flash_fw.c @@ -0,0 +1,125 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include <avr32/io.h> + +#include "printf-stdarg.h" +#include "wl_fw.h" +#include "startup.h" +#include "nor_flash.h" +#include "gpio.h" + +#define GREEN_OFF() gpio_set_gpio_pin(LED0_GPIO) +#define GREEN_ON() gpio_clr_gpio_pin(LED0_GPIO) +#define GREEN_BLINK() gpio_tgl_gpio_pin(LED0_GPIO) +#define RED_OFF() gpio_set_gpio_pin(LED1_GPIO) +#define RED_ON() gpio_clr_gpio_pin(LED1_GPIO) +#define RED_BLINK() gpio_tgl_gpio_pin(LED1_GPIO) +#define BLUE_OFF() gpio_set_gpio_pin(LED2_GPIO) +#define BLUE_ON() gpio_clr_gpio_pin(LED2_GPIO) +#define BLUE_BLINK() gpio_tgl_gpio_pin(LED2_GPIO) + + +/** + * + */ +void +led_init(void) +{ + gpio_enable_gpio_pin(LED0_GPIO); + gpio_enable_gpio_pin(LED1_GPIO); + gpio_enable_gpio_pin(LED2_GPIO); + GREEN_OFF(); + RED_OFF(); + BLUE_OFF(); +} + + +int main(void) +{ + U32 pos, len; + + startup_init(); + printk("*** HD chip firmware upgrade ver 2.7 ***\n"); + led_init(); + flash_init(); + GREEN_ON(); + if (at45dbx_mem_check() == OK) + { + printk("Memory check... [ OK ]\n"); + } + else + { + RED_ON(); + GREEN_OFF(); + printk("Memory check... [FAIL]\n"); + return 0; + } + printk("Writing firmware data to flash\n"); + pos = 0; + while (pos < fw_len) { + if (fw_len - pos > SECTOR_SIZE) + len = SECTOR_SIZE; + else + len = fw_len - pos; + + flash_write(pos, fw_buf + pos, len); + pos += len; + } + + printk("Verifying firmware data\n"); + pos = 0; + while (pos < fw_len) { + static U8 page_buf[SECTOR_SIZE]; + U32 i; + + if (fw_len - pos > SECTOR_SIZE) + len = SECTOR_SIZE; + else + len = fw_len - pos; + + flash_read(pos, page_buf, len); + + for (i = 0; i < len; i++) + if (*(page_buf + i) != *(fw_buf + pos + i)) { + RED_ON(); + GREEN_OFF(); + printk("Verify failed at byte %d, 0x%02x != 0x%02x\n", + pos + i, *(page_buf + i), *(fw_buf + pos + i)); + return 0; + } + + + pos += len; + } + GREEN_OFF(); + BLUE_ON(); + printk("Firmware successfully stored in flash!\n"); + return 0; +} diff --git a/firmwares/wifishield/wifi_dnld/src/license.txt b/firmwares/wifishield/wifi_dnld/src/license.txt new file mode 100644 index 0000000..e57439f --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/license.txt @@ -0,0 +1,42 @@ + Copyright (C) 2009, H&D Wireless AB All rights reserved. + + The license to use this software in whole and in part and to + redistribute it in any form follows with the WiFi HW module from H&D + Wireless and is granted under the following restrictions: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. The name of H&D Wireless AB may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + 4. The software may only be used together with hardware from H&D + Wireless all other use is prohibited. + + 5. The license to use and redistribute the software is granted + together with the purchase of a hardware platform on a one to one + basis + + 6. The binary code may not be reversed engineered or by other means + copied to circumvent this license. + + THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT + SHALL HD WIRELESS AB BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + OF THE POSSIBILITY OF SUCH DAMAGE. + + For more information regarding this software license Contact H&D + Wireless AB (support@hd-wireless.se). diff --git a/firmwares/wifishield/wifi_dnld/src/nor_flash.c b/firmwares/wifishield/wifi_dnld/src/nor_flash.c new file mode 100644 index 0000000..0115949 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/nor_flash.c @@ -0,0 +1,99 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include <string.h> +#include "compiler.h" +#include "preprocessor.h" +#include "board.h" +#include "power_clocks_lib.h" +#include "gpio.h" +#include "spi.h" +#include "conf_at45dbx.h" +#include "at45dbx.h" +#include "clocks.h" + + +void flash_init(void) +{ + static const gpio_map_t AT45DBX_SPI_GPIO_MAP = { + { AT45DBX_SPI_SCK_PIN, AT45DBX_SPI_SCK_FUNCTION }, + { AT45DBX_SPI_MISO_PIN, AT45DBX_SPI_MISO_FUNCTION }, + { AT45DBX_SPI_MOSI_PIN, AT45DBX_SPI_MOSI_FUNCTION }, + { AT45DBX_SPI_NPCS2_PIN, AT45DBX_SPI_NPCS2_FUNCTION }, + }; + + spi_options_t spiOptions = { + .reg = AT45DBX_SPI_FIRST_NPCS, + .baudrate = AT45DBX_SPI_MASTER_SPEED, + .bits = AT45DBX_SPI_BITS, + .spck_delay = 0, + .trans_delay = 0, + .stay_act = 1, + .spi_mode = 0, + .modfdis = 1 + }; + + gpio_enable_module(AT45DBX_SPI_GPIO_MAP, + sizeof(AT45DBX_SPI_GPIO_MAP) / + sizeof(AT45DBX_SPI_GPIO_MAP[0])); + + spi_initMaster(AT45DBX_SPI, &spiOptions); + + spi_selectionMode(AT45DBX_SPI, 0, 0, 0); + spi_enable(AT45DBX_SPI); + + /* put up flash reset pin */ + gpio_set_gpio_pin(AT45DBX_CHIP_RESET); + + at45dbx_init(spiOptions, FPBA_HZ); +} + +void flash_write(U32 addr, const U8* buf, U32 len) +{ + U32 sector = addr / AT45DBX_SECTOR_SIZE; + U32 i; + Assert(addr % AT45DBX_SECTOR_SIZE == 0); + + at45dbx_write_open(sector); + for (i = 0; i < len; i++) + at45dbx_write_byte(buf[i]); + at45dbx_write_close(); +} + +void flash_read(U32 addr, U8* buf, U32 len) +{ + U32 sector = addr / AT45DBX_SECTOR_SIZE; + U32 i; + Assert(addr % AT45DBX_SECTOR_SIZE == 0); + + at45dbx_read_open(sector); + for (i = 0; i < len; i++) + buf[i] = at45dbx_read_byte(); + at45dbx_read_close(); +} diff --git a/firmwares/wifishield/wifi_dnld/src/nor_flash.h b/firmwares/wifishield/wifi_dnld/src/nor_flash.h new file mode 100644 index 0000000..52a4a20 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/nor_flash.h @@ -0,0 +1,41 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef NOR_FLASH_H +#define NOR_FLASH_H + +#include "at45dbx.h" + +#define SECTOR_SIZE AT45DBX_SECTOR_SIZE + +void flash_init(void); +void flash_write(U32 addr, const U8* buf, U32 len); +void flash_read(U32 addr, U8* buf, U32 len); + +#endif diff --git a/firmwares/wifishield/wifi_dnld/src/printf-stdarg.c b/firmwares/wifishield/wifi_dnld/src/printf-stdarg.c new file mode 100644 index 0000000..86ab88e --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/printf-stdarg.c @@ -0,0 +1,323 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/* This source file is part of the ATMEL AVR32-SoftwareFramework-AT32UC3A-1.4.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief sprintf functions to replace newlib for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + Copyright 2001, 2002 Georges Menie (www.menie.org) + stdarg version contributed by Christian Ettinger + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +/* + putchar is the only external dependency for this file, + if you have a working putchar, leave it commented out. + If not, uncomment the define below and + replace outbyte(c) by your own function call. + +*/ + + +#include <sys/reent.h> +#include <stdarg.h> + +#define putchar(c) print_dbg_char(c) + +static void printchar(char **str, int c) +{ + extern int putchar(int c); + + if (str) { + **str = c; + ++(*str); + } + else (void)putchar(c); +} + +#define PAD_RIGHT 1 +#define PAD_ZERO 2 + +static int prints(char **out, const char *string, int width, int pad) +{ + register int pc = 0, padchar = ' '; + + if (width > 0) { + register int len = 0; + register const char *ptr; + for (ptr = string; *ptr; ++ptr) ++len; + if (len >= width) width = 0; + else width -= len; + if (pad & PAD_ZERO) padchar = '0'; + } + if (!(pad & PAD_RIGHT)) { + for ( ; width > 0; --width) { + printchar (out, padchar); + ++pc; + } + } + for ( ; *string ; ++string) { + printchar (out, *string); + ++pc; + } + for ( ; width > 0; --width) { + printchar (out, padchar); + ++pc; + } + + return pc; +} + +/* the following should be enough for 32 bit int */ +#define PRINT_BUF_LEN 12 + +static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase) +{ + char print_buf[PRINT_BUF_LEN]; + register char *s; + register int t, neg = 0, pc = 0; + register unsigned int u = i; + + if (i == 0) { + print_buf[0] = '0'; + print_buf[1] = '\0'; + return prints (out, print_buf, width, pad); + } + + if (sg && b == 10 && i < 0) { + neg = 1; + u = -i; + } + + s = print_buf + PRINT_BUF_LEN-1; + *s = '\0'; + + while (u) { + t = u % b; + if( t >= 10 ) + t += letbase - '0' - 10; + *--s = t + '0'; + u /= b; + } + + if (neg) { + if( width && (pad & PAD_ZERO) ) { + printchar (out, '-'); + ++pc; + --width; + } + else { + *--s = '-'; + } + } + + return pc + prints (out, s, width, pad); +} + +int fprintf(__FILE *stream, const char *format, ...) +{ +return 0; +} +int printk_va(char **out, const char *format, va_list args ) +{ + register int width, pad; + register int pc = 0; + char scr[2]; + + for (; *format != 0; ++format) { + if (*format == '%') { + ++format; + width = pad = 0; + if (*format == '\0') break; + if (*format == '%') goto out; + if (*format == '-') { + ++format; + pad = PAD_RIGHT; + } + while (*format == '0') { + ++format; + pad |= PAD_ZERO; + } + for ( ; *format >= '0' && *format <= '9'; ++format) { + width *= 10; + width += *format - '0'; + } + if( *format == 's' ) { + register char *s = (char *)va_arg( args, int ); + pc += prints (out, s?s:"(null)", width, pad); + continue; + } + if( *format == 'd' ) { + pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a'); + continue; + } + if( *format == 'p' ) { + pad = 8; + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a'); + continue; + } + if( *format == 'x' ) { + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a'); + continue; + } + if( *format == 'X' ) { + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A'); + continue; + } + if( *format == 'u' ) { + pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a'); + continue; + } + if( *format == 'c' ) { + /* char are converted to int then pushed on the stack */ + scr[0] = (char)va_arg( args, int ); + scr[1] = '\0'; + pc += prints (out, scr, width, pad); + continue; + } + } + else { + out: + printchar (out, *format); + ++pc; + } + } + if (out) **out = '\0'; + va_end( args ); + return pc; +} + +int printk(const char *format, ...) +{ + va_list args; + + va_start( args, format ); + return printk_va( 0, format, args ); +} + +int sprintf(char *out, const char *format, ...) +{ + va_list args; + + va_start( args, format ); + return printk_va( &out, format, args ); +} + +#ifdef TEST_PRINTF +int main(void) +{ + char *ptr = "Hello world!"; + char *np = 0; + int i = 5; + unsigned int bs = sizeof(int)*8; + int mi; + char buf[80]; + + mi = (1 << (bs-1)) + 1; + printf("%s\n", ptr); + printf("printf test\n"); + printf("%s is null pointer\n", np); + printf("%d = 5\n", i); + printf("%d = - max int\n", mi); + printf("char %c = 'a'\n", 'a'); + printf("hex %x = ff\n", 0xff); + printf("hex %02x = 00\n", 0); + printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3); + printf("%d %s(s)%", 0, "message"); + printf("\n"); + printf("%d %s(s) with %%\n", 0, "message"); + sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf); + sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf); + sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf); + sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf); + sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf); + sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf); + sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf); + sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf); + + return 0; +} + +/* + * if you compile this file with + * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c + * you will get a normal warning: + * printf.c:214: warning: spurious trailing `%' in format + * this line is testing an invalid % at the end of the format string. + * + * this should display (on 32bit int machine) : + * + * Hello world! + * printf test + * (null) is null pointer + * 5 = 5 + * -2147483647 = - max int + * char a = 'a' + * hex ff = ff + * hex 00 = 00 + * signed -3 = unsigned 4294967293 = hex fffffffd + * 0 message(s) + * 0 message(s) with % + * justif: "left " + * justif: " right" + * 3: 0003 zero padded + * 3: 3 left justif. + * 3: 3 right justif. + * -3: -003 zero padded + * -3: -3 left justif. + * -3: -3 right justif. + */ + +#endif diff --git a/firmwares/wifishield/wifi_dnld/src/printf-stdarg.h b/firmwares/wifishield/wifi_dnld/src/printf-stdarg.h new file mode 100644 index 0000000..f6bd664 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/printf-stdarg.h @@ -0,0 +1,36 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef PRINTF_STDARG_H +#define PRINTF_STDARG_H +#include <stdarg.h> + +int printk(const char *format, ...); +int printk_va(char **out, const char *format, va_list args ); +#endif diff --git a/firmwares/wifishield/wifi_dnld/src/startup.c b/firmwares/wifishield/wifi_dnld/src/startup.c new file mode 100644 index 0000000..fa2a8c0 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/startup.c @@ -0,0 +1,75 @@ +/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "startup.h" +#include "pm.h" +#include "intc.h" +#include "board.h" +#include "print_funcs.h" +#include "clocks.h" + + +static void init_exceptions(void) +{ + extern void _evba; + Set_system_register(AVR32_EVBA, (int)&_evba); + Enable_global_exception(); +} + +static void init_hmatrix(void) +{ + union { + unsigned long scfg; + avr32_hmatrix_scfg_t SCFG; + } u_avr32_hmatrix_scfg = { + AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH] + }; + u_avr32_hmatrix_scfg.SCFG.defmstr_type = + AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT; + AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH] = + u_avr32_hmatrix_scfg.scfg; +} + +static void init_interrupts(void) +{ + INTC_init_interrupts(); + + //initExtInt(); + + Enable_global_interrupt(); +} + +void startup_init(void) +{ + init_exceptions(); + init_hmatrix(); + init_sys_clocks(); + init_interrupts(); + init_dbg_rs232(FPBA_HZ); +} diff --git a/firmwares/wifishield/wifi_dnld/src/startup.h b/firmwares/wifishield/wifi_dnld/src/startup.h new file mode 100644 index 0000000..a9adc60 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/startup.h @@ -0,0 +1,35 @@ +/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */ + +/*! \page License + * Copyright (C) 2009, H&D Wireless AB All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of H&D Wireless AB may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef STARTUP_H +#define STARTUP_H + +void startup_init(void); + +#endif diff --git a/firmwares/wifishield/wifi_dnld/src/wl_fw.h b/firmwares/wifishield/wifi_dnld/src/wl_fw.h new file mode 100644 index 0000000..5be5f37 --- /dev/null +++ b/firmwares/wifishield/wifi_dnld/src/wl_fw.h @@ -0,0 +1,19287 @@ +/* + * Programming interface for wl_api. + * Copyright (C) 2010 HD Wireless AB + * + * You should have received a copy of the license along with this library. + */ + +#ifndef WITHOUT_STDINT +#include <stdint.h> +#endif +const uint8_t fw_buf[154188] = { + 0x10, 0x61, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x30, 0x00, 0x00, 0x00, 0x10, 0x61, 0x04, 0x00, + 0x38, 0x61, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x20, 0x61, 0x04, 0x00, + 0x30, 0x61, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x30, 0x61, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x10, 0x61, 0x04, 0x00, + 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0xee, 0xee, + 0xee, 0xee, 0x18, 0xf0, 0x9f, 0xe5, 0x18, 0xf0, + 0x9f, 0xe5, 0x18, 0xf0, 0x9f, 0xe5, 0x18, 0xf0, + 0x9f, 0xe5, 0x00, 0x00, 0xa0, 0xe1, 0x18, 0xf0, + 0x9f, 0xe5, 0x18, 0xf0, 0x9f, 0xe5, 0x44, 0x00, + 0x00, 0x00, 0xb4, 0x08, 0x00, 0x00, 0xb4, 0x08, + 0x00, 0x00, 0xb4, 0x08, 0x00, 0x00, 0xb4, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x08, + 0x00, 0x00, 0x3c, 0x00, 0x3c, 0x00, 0x00, 0x00, + 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0f, 0xe1, 0x1f, 0x00, 0xc0, 0xe3, + 0x13, 0x00, 0x80, 0xe3, 0xc0, 0x00, 0x80, 0xe3, + 0x00, 0xf0, 0x2f, 0xe1, 0x1c, 0xf0, 0x9f, 0xe5, + 0x3d, 0x02, 0x00, 0xeb, 0x5a, 0x02, 0x00, 0xeb, + 0x8d, 0x02, 0x00, 0xeb, 0x01, 0x00, 0x8f, 0xe2, + 0x10, 0xff, 0x2f, 0xe1, 0x41, 0xf0, 0xde, 0xfb, + 0x01, 0xf0, 0xdc, 0xfd, 0x3c, 0x00, 0x78, 0x00, + 0x00, 0x00, 0xfe, 0xe7, 0x00, 0x00, 0x5c, 0x00, + 0x00, 0x00, 0x78, 0x47, 0xc0, 0x46, 0x01, 0x00, + 0x00, 0xea, 0x78, 0x47, 0xc0, 0x46, 0x17, 0x00, + 0x00, 0xea, 0x8c, 0x11, 0x9f, 0xe5, 0x00, 0x20, + 0x91, 0xe5, 0x00, 0x30, 0x0f, 0xe1, 0x84, 0x11, + 0x9f, 0xe5, 0xfd, 0x20, 0xa1, 0xe8, 0x80, 0x01, + 0x9f, 0xe5, 0x80, 0x21, 0x9f, 0xe5, 0x01, 0x20, + 0x42, 0xe0, 0x0d, 0x00, 0x40, 0xe0, 0x3c, 0x00, + 0xb4, 0x00, 0x00, 0x00, 0x02, 0x00, 0x50, 0xe1, + 0x28, 0x00, 0x00, 0xaa, 0x68, 0x01, 0x9f, 0xe5, + 0x0d, 0x00, 0x50, 0xe1, 0x02, 0x00, 0x00, 0xba, + 0x04, 0x20, 0x10, 0xe4, 0x04, 0x20, 0x81, 0xe4, + 0xfa, 0xff, 0xff, 0xea, 0x58, 0x11, 0x9f, 0xe5, + 0x58, 0x01, 0x9f, 0xe5, 0x00, 0x00, 0x81, 0xe5, + 0x3c, 0x11, 0x9f, 0xe5, 0x50, 0x01, 0x9f, 0xe5, + 0x00, 0x00, 0x81, 0xe5, 0x1e, 0xff, 0x2f, 0xe1, + 0x3c, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x48, 0x11, + 0x9f, 0xe5, 0x00, 0x00, 0x91, 0xe5, 0x24, 0x11, + 0x9f, 0xe5, 0x00, 0x00, 0x81, 0xe5, 0x2c, 0x11, + 0x9f, 0xe5, 0x38, 0x01, 0x9f, 0xe5, 0x00, 0x00, + 0x81, 0xe5, 0x1e, 0xff, 0x2f, 0xe1, 0x74, 0x02, + 0x00, 0xeb, 0x10, 0x01, 0x9f, 0xe5, 0x28, 0x11, + 0x9f, 0xe5, 0x04, 0x20, 0x91, 0xe4, 0x04, 0x20, + 0x00, 0xe4, 0x04, 0x21, 0x9f, 0xe5, 0x02, 0x00, + 0x51, 0xe1, 0x3c, 0x00, 0x2c, 0x01, 0x00, 0x00, + 0xfa, 0xff, 0xff, 0x1a, 0xf0, 0x10, 0x9f, 0xe5, + 0xfd, 0x20, 0xb1, 0xe8, 0x03, 0xf0, 0x2f, 0xe1, + 0xe0, 0x10, 0x9f, 0xe5, 0x00, 0x20, 0x81, 0xe5, + 0xe8, 0x10, 0x9f, 0xe5, 0xf4, 0x20, 0x9f, 0xe5, + 0x00, 0x20, 0x81, 0xe5, 0x02, 0x10, 0x80, 0xe2, + 0x00, 0x00, 0x20, 0xe0, 0x01, 0x00, 0x40, 0xe2, + 0x11, 0xff, 0x2f, 0xe1, 0x01, 0x00, 0x8f, 0xe2, + 0x10, 0xff, 0x2f, 0xe1, 0x3c, 0x00, 0x68, 0x01, + 0x00, 0x00, 0x01, 0xf0, 0x9c, 0xf8, 0x78, 0x47, + 0x00, 0x00, 0x01, 0x00, 0x8f, 0xe2, 0x10, 0xff, + 0x2f, 0xe1, 0x01, 0xf0, 0x94, 0xf8, 0x78, 0x47, + 0x00, 0x00, 0x03, 0x00, 0x2d, 0xe9, 0x00, 0x10, + 0x0f, 0xe1, 0x00, 0x10, 0x80, 0xe5, 0xb8, 0x10, + 0x9f, 0xe5, 0x04, 0x10, 0x80, 0xe5, 0x00, 0x10, + 0xa0, 0xe1, 0x10, 0x00, 0x80, 0xe2, 0xfc, 0x1f, + 0xa0, 0xe8, 0x00, 0x20, 0xa0, 0xe1, 0x3c, 0x00, + 0xa4, 0x01, 0x00, 0x00, 0x01, 0x30, 0xa0, 0xe1, + 0x03, 0x00, 0xbd, 0xe8, 0x08, 0x00, 0x83, 0xe5, + 0x0c, 0x10, 0x83, 0xe5, 0xd3, 0x00, 0xa0, 0xe3, + 0x00, 0xf0, 0x21, 0xe1, 0x00, 0x60, 0xa2, 0xe8, + 0x00, 0x10, 0x4f, 0xe1, 0x04, 0x10, 0x82, 0xe4, + 0xd2, 0x00, 0xa0, 0xe3, 0x00, 0xf0, 0x21, 0xe1, + 0x00, 0x60, 0xa2, 0xe8, 0x00, 0x10, 0x4f, 0xe1, + 0x04, 0x10, 0x82, 0xe4, 0xd1, 0x00, 0xa0, 0xe3, + 0x3c, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0xf0, + 0x21, 0xe1, 0x00, 0x7f, 0xa2, 0xe8, 0x00, 0x10, + 0x4f, 0xe1, 0x04, 0x10, 0x82, 0xe4, 0xd7, 0x00, + 0xa0, 0xe3, 0x00, 0xf0, 0x21, 0xe1, 0x00, 0x60, + 0xa2, 0xe8, 0x00, 0x10, 0x4f, 0xe1, 0x04, 0x10, + 0x82, 0xe4, 0xdb, 0x00, 0xa0, 0xe3, 0x00, 0xf0, + 0x21, 0xe1, 0x00, 0x60, 0xa2, 0xe8, 0x00, 0x10, + 0x4f, 0xe1, 0x00, 0x10, 0x82, 0xe5, 0x00, 0x00, + 0x93, 0xe5, 0x3c, 0x00, 0x1c, 0x02, 0x00, 0x00, + 0x00, 0xf0, 0x2f, 0xe1, 0x1e, 0xff, 0x2f, 0xe1, + 0x20, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, + 0x20, 0xee, 0x01, 0x00, 0xd8, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x18, 0xf0, 0x9f, 0xe5, + 0x10, 0x01, 0x00, 0x00, 0x08, 0x03, 0x00, 0x00, + 0xee, 0xee, 0xee, 0xee, 0x24, 0x03, 0x00, 0x00, + 0x20, 0x02, 0x00, 0x00, 0xb0, 0xb5, 0x04, 0x1c, + 0x63, 0x1c, 0x0b, 0x4d, 0x3c, 0x00, 0x58, 0x02, + 0x00, 0x00, 0x01, 0xd1, 0x6c, 0x69, 0x10, 0xe0, + 0x00, 0xf0, 0x6c, 0xfb, 0x09, 0x48, 0xff, 0xf7, + 0x0c, 0xff, 0xec, 0x60, 0x08, 0x4a, 0x51, 0x68, + 0x50, 0x68, 0x88, 0x42, 0xfc, 0xd0, 0x02, 0x20, + 0x28, 0x70, 0x01, 0x21, 0x8a, 0x20, 0x01, 0xf0, + 0x12, 0xf8, 0x20, 0x1c, 0xb0, 0xbd, 0x30, 0x00, + 0x07, 0x00, 0x51, 0x02, 0x00, 0x00, 0x00, 0x03, + 0x07, 0x00, 0xb0, 0xb5, 0x05, 0x1c, 0x3c, 0x00, + 0x94, 0x02, 0x00, 0x00, 0x00, 0x24, 0x00, 0xf0, + 0x50, 0xfb, 0x14, 0x48, 0xff, 0xf7, 0xf0, 0xfe, + 0x13, 0x49, 0x14, 0x48, 0xc1, 0x60, 0x01, 0x21, + 0x13, 0x4a, 0x49, 0x03, 0x91, 0x60, 0x13, 0x49, + 0xca, 0x78, 0x08, 0x23, 0x9a, 0x43, 0xca, 0x70, + 0xca, 0x78, 0x04, 0x23, 0x1a, 0x43, 0xca, 0x70, + 0x6b, 0x1c, 0x0d, 0xd0, 0x0e, 0x4b, 0x5a, 0x68, + 0x59, 0x68, 0x91, 0x42, 0xfc, 0xd0, 0xbe, 0x21, + 0x3c, 0x00, 0xd0, 0x02, 0x00, 0x00, 0x19, 0x73, + 0x19, 0x7a, 0x11, 0x22, 0x91, 0x43, 0x19, 0x72, + 0x19, 0x7a, 0xc9, 0x07, 0xfc, 0xd4, 0x02, 0x21, + 0x01, 0x70, 0xff, 0xf7, 0xd0, 0xfe, 0x20, 0x1c, + 0xb0, 0xbd, 0x91, 0x02, 0x00, 0x00, 0xff, 0xff, + 0xff, 0x00, 0x30, 0x00, 0x07, 0x00, 0x00, 0x10, + 0x07, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x03, + 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x3c, 0x00, 0x0c, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x48, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, + 0x84, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x3c, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, + 0x08, 0x47, 0x10, 0x47, 0x18, 0x47, 0x20, 0x47, + 0x28, 0x47, 0x30, 0x47, 0x38, 0x47, 0x10, 0xb5, + 0x04, 0x1c, 0x10, 0x1c, 0x00, 0xf0, 0x23, 0xf9, + 0x03, 0xc4, 0x10, 0xbc, 0x08, 0xbc, 0x18, 0x47, + 0x00, 0x00, 0x3c, 0x00, 0xfc, 0x03, 0x00, 0x00, + 0x10, 0xb4, 0x04, 0x2a, 0x0e, 0xd3, 0x03, 0x1c, + 0x0b, 0x43, 0x9b, 0x07, 0x0a, 0xd1, 0x08, 0xc8, + 0x10, 0xc9, 0xa3, 0x42, 0x02, 0xd1, 0x04, 0x3a, + 0x04, 0x2a, 0xf8, 0xd2, 0xa3, 0x42, 0x01, 0xd0, + 0x04, 0x38, 0x04, 0x39, 0x00, 0x2a, 0x02, 0xd1, + 0x00, 0x20, 0x10, 0xbc, 0x70, 0x47, 0xd3, 0x07, + 0x01, 0xd5, 0x01, 0x32, 0x05, 0xe0, 0x03, 0x78, + 0x0c, 0x78, 0x01, 0x31, 0x3c, 0x00, 0x38, 0x04, + 0x00, 0x00, 0x01, 0x30, 0xa3, 0x42, 0x07, 0xd1, + 0x03, 0x78, 0x0c, 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