diff options
Diffstat (limited to 'libraries/Wire/src')
| -rw-r--r-- | libraries/Wire/src/Wire.cpp | 4 | ||||
| -rw-r--r-- | libraries/Wire/src/utility/twi.c | 10 |
2 files changed, 7 insertions, 7 deletions
diff --git a/libraries/Wire/src/Wire.cpp b/libraries/Wire/src/Wire.cpp index c407776..001d924 100644 --- a/libraries/Wire/src/Wire.cpp +++ b/libraries/Wire/src/Wire.cpp @@ -100,7 +100,7 @@ void TwoWire::setClock(uint32_t clock) * when `clearWireTimeoutFlag()` or `setWireTimeoutUs()` is called. * * Note that this timeout can also trigger while waiting for clock stretching or waiting for a second master - * to complete its transaction. So make sure to adapt the timeout to accomodate for those cases if needed. + * to complete its transaction. So make sure to adapt the timeout to accommodate for those cases if needed. * A typical timeout would be 25ms (which is the maximum clock stretching allowed by the SMBus protocol), * but (much) shorter values will usually also work. * @@ -120,7 +120,7 @@ void TwoWire::setWireTimeout(uint32_t timeout, bool reset_with_timeout){ /*** * Returns the TWI timeout flag. * - * @return true if timeout has occured since the flag was last cleared. + * @return true if timeout has occurred since the flag was last cleared. */ bool TwoWire::getWireTimeoutFlag(void){ return(twi_manageTimeoutFlag(false)); diff --git a/libraries/Wire/src/utility/twi.c b/libraries/Wire/src/utility/twi.c index d223760..e09a33c 100644 --- a/libraries/Wire/src/utility/twi.c +++ b/libraries/Wire/src/utility/twi.c @@ -175,7 +175,7 @@ uint8_t twi_readFrom(uint8_t address, uint8_t* data, uint8_t length, uint8_t sen } twi_state = TWI_MRX; twi_sendStop = sendStop; - // reset error state (0xFF.. no error occured) + // reset error state (0xFF.. no error occurred) twi_error = 0xFF; // initialize buffer iteration vars @@ -183,7 +183,7 @@ uint8_t twi_readFrom(uint8_t address, uint8_t* data, uint8_t length, uint8_t sen twi_masterBufferLength = length-1; // This is not intuitive, read on... // On receive, the previously configured ACK/NACK setting is transmitted in // response to the received byte before the interrupt is signalled. - // Therefor we must actually set NACK when the _next_ to last byte is + // Therefore we must actually set NACK when the _next_ to last byte is // received, causing that NACK to be sent in response to receiving the last // expected byte of data. @@ -269,7 +269,7 @@ uint8_t twi_writeTo(uint8_t address, uint8_t* data, uint8_t length, uint8_t wait } twi_state = TWI_MTX; twi_sendStop = sendStop; - // reset error state (0xFF.. no error occured) + // reset error state (0xFF.. no error occurred) twi_error = 0xFF; // initialize buffer iteration vars @@ -294,7 +294,7 @@ uint8_t twi_writeTo(uint8_t address, uint8_t* data, uint8_t length, uint8_t wait // We need to remove ourselves from the repeated start state before we enable interrupts, // since the ISR is ASYNC, and we could get confused if we hit the ISR before cleaning // up. Also, don't enable the START interrupt. There may be one pending from the - // repeated start that we sent outselves, and that would really confuse things. + // repeated start that we sent ourselves, and that would really confuse things. twi_inRepStart = false; // remember, we're dealing with an ASYNC ISR startMicros = micros(); do { @@ -411,7 +411,7 @@ void twi_stop(void) // send stop condition TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWEA) | _BV(TWINT) | _BV(TWSTO); - // wait for stop condition to be exectued on bus + // wait for stop condition to be executed on bus // TWINT is not set after a stop condition! // We cannot use micros() from an ISR, so approximate the timeout with cycle-counted delays const uint8_t us_per_loop = 8; |