diff options
| author | David A. Mellis <d.mellis@arduino.cc> | 2011-01-15 13:29:08 +0000 |
|---|---|---|
| committer | David A. Mellis <d.mellis@arduino.cc> | 2011-01-15 13:29:08 +0000 |
| commit | 7a66c18e70ae097f47654bd63d6172bb6452a384 (patch) | |
| tree | 8cbfbc2e713cebdad1e37e4711586fad22862543 /bootloaders/optiboot/optiboot.c | |
| parent | 11dd06436d6144420cc6f5b5d9a926e7f34818b1 (diff) | |
Fix to optiboot infinite loop problem.
Explicitly setting R1 to 0 so that the watchdog timer is properly initializing, preventing it from timing out and resetting the processor.
http://code.google.com/p/optiboot/issues/detail?id=26
http://code.google.com/p/arduino/issues/detail?id=446
Diffstat (limited to 'bootloaders/optiboot/optiboot.c')
| -rw-r--r-- | bootloaders/optiboot/optiboot.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bootloaders/optiboot/optiboot.c b/bootloaders/optiboot/optiboot.c index af92995..c7d817a 100644 --- a/bootloaders/optiboot/optiboot.c +++ b/bootloaders/optiboot/optiboot.c @@ -213,7 +213,7 @@ int main(void) { // If not, uncomment the following instructions: // cli(); // SP=RAMEND; // This is done by hardware reset - // asm volatile ("clr __zero_reg__"); + asm volatile ("clr __zero_reg__"); uint8_t ch; |