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authorJohn Holman <john.g.holman@gmail.com>2017-10-25 11:07:35 +0100
committerMartino Facchin <m.facchin@arduino.cc>2017-11-13 17:46:47 +0100
commit58006613a7c858417881744419c5da54cc21a401 (patch)
tree91ab55b89da9ccf73b732117ad6230c3178d5916 /cores
parent99c294c5a251cffe84a51d474ec5275bd1a8311c (diff)
Fix flush hanging issue
Make write to UDR and clearing of TXC bit in flush() atomic to avoid race condition. Fixes #3745 (second different issue introduced later but discussed in the same issue)
Diffstat (limited to 'cores')
-rw-r--r--cores/arduino/HardwareSerial.cpp14
1 files changed, 12 insertions, 2 deletions
diff --git a/cores/arduino/HardwareSerial.cpp b/cores/arduino/HardwareSerial.cpp
index e6ccdef..ecd7918 100644
--- a/cores/arduino/HardwareSerial.cpp
+++ b/cores/arduino/HardwareSerial.cpp
@@ -226,8 +226,18 @@ size_t HardwareSerial::write(uint8_t c)
// significantly improve the effective datarate at high (>
// 500kbit/s) bitrates, where interrupt overhead becomes a slowdown.
if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) {
- *_udr = c;
- *_ucsra = ((*_ucsra) & ((1 << U2X0) | (1 << MPCM0))) | (1 << TXC0);
+ // If TXC is cleared before writing UDR and the previous byte
+ // completes before writing to UDR, TXC will be set but a byte
+ // is still being transmitted causing flush() to return too soon.
+ // So writing UDR must happen first.
+ // Writing UDR and clearing TC must be done atomically, otherwise
+ // interrupts might delay the TXC clear so the byte written to UDR
+ // is transmitted (setting TXC) before clearing TXC. Then TXC will
+ // be cleared when no bytes are left, causing flush() to hang
+ ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
+ *_udr = c;
+ *_ucsra = ((*_ucsra) & ((1 << U2X0) | (1 << MPCM0))) | (1 << TXC0);
+ }
return 1;
}
tx_buffer_index_t i = (_tx_buffer_head + 1) % SERIAL_TX_BUFFER_SIZE;