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authorMatthijs Kooijman <matthijs@stdin.nl>2013-04-18 19:06:00 +0200
committerCristian Maglie <c.maglie@bug.st>2014-01-22 09:38:25 +0100
commitf1cd85da7ad0030d1fb1102aa9e3119851e1c4aa (patch)
tree56d5bab27019e6d38f1cdab189eed556eda47183 /cores/arduino
parentdbe23685c27cb1467dc84140e4899a0bf8e23248 (diff)
Disable the UDRE interrupt sooner in HardwareSerial
Before, the interrupt was disabled when it was triggered and it turned out there was no data to send. However, the interrupt can be disabled already when the last byte is written to the UART, since write() will always re-enable the interrupt when it adds new data to the buffer. Closes: #1008
Diffstat (limited to 'cores/arduino')
-rw-r--r--cores/arduino/HardwareSerial.cpp24
1 files changed, 12 insertions, 12 deletions
diff --git a/cores/arduino/HardwareSerial.cpp b/cores/arduino/HardwareSerial.cpp
index ffdb82c..9a02f23 100644
--- a/cores/arduino/HardwareSerial.cpp
+++ b/cores/arduino/HardwareSerial.cpp
@@ -223,22 +223,22 @@ void HardwareSerial::_rx_complete_irq(void)
void HardwareSerial::_tx_udr_empty_irq(void)
{
+ // If interrupts are enabled, there must be more data in the output
+ // buffer. Send the next byte
+ unsigned char c = _tx_buffer[_tx_buffer_tail];
+ _tx_buffer_tail = (_tx_buffer_tail + 1) % SERIAL_BUFFER_SIZE;
+
+ *_udr = c;
+
+ // clear the TXC bit -- "can be cleared by writing a one to its bit
+ // location". This makes sure flush() won't return until the bytes
+ // actually got written
+ sbi(*_ucsra, TXC0);
+
if (_tx_buffer_head == _tx_buffer_tail) {
// Buffer empty, so disable interrupts
cbi(*_ucsrb, UDRIE0);
}
- else {
- // There is more data in the output buffer. Send the next byte
- unsigned char c = _tx_buffer[_tx_buffer_tail];
- _tx_buffer_tail = (_tx_buffer_tail + 1) % SERIAL_BUFFER_SIZE;
-
- *_udr = c;
-
- // clear the TXC bit -- "can be cleared by writing a one to its bit
- // location". This makes sure flush() won't return until the bytes
- // actually got written
- sbi(*_ucsra, TXC0);
- }
}
// Constructors ////////////////////////////////////////////////////////////////