From 68e9d04f91aa26daa4e3c701002610f2352039fd Mon Sep 17 00:00:00 2001 From: "David A. Mellis" Date: Sat, 8 Nov 2008 21:31:12 +0000 Subject: Waiting for pulse to start (rising or falling edge) to start timing. --- cores/arduino/wiring_pulse.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'cores/arduino/wiring_pulse.c') diff --git a/cores/arduino/wiring_pulse.c b/cores/arduino/wiring_pulse.c index 0157114..8f232f1 100755 --- a/cores/arduino/wiring_pulse.c +++ b/cores/arduino/wiring_pulse.c @@ -44,6 +44,11 @@ unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout) unsigned long numloops = 0; unsigned long maxloops = microsecondsToClockCycles(timeout) / 16; + // wait for any previous pulse to end + while ((*portInputRegister(port) & bit) == stateMask) + if (numloops++ == maxloops) + return 0; + // wait for the pulse to start while ((*portInputRegister(port) & bit) != stateMask) if (numloops++ == maxloops) -- cgit v1.2.3-18-g5258