From 7a66c18e70ae097f47654bd63d6172bb6452a384 Mon Sep 17 00:00:00 2001 From: "David A. Mellis" Date: Sat, 15 Jan 2011 13:29:08 +0000 Subject: Fix to optiboot infinite loop problem. Explicitly setting R1 to 0 so that the watchdog timer is properly initializing, preventing it from timing out and resetting the processor. http://code.google.com/p/optiboot/issues/detail?id=26 http://code.google.com/p/arduino/issues/detail?id=446 --- bootloaders/optiboot/optiboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'bootloaders/optiboot/optiboot.c') diff --git a/bootloaders/optiboot/optiboot.c b/bootloaders/optiboot/optiboot.c index af92995..c7d817a 100644 --- a/bootloaders/optiboot/optiboot.c +++ b/bootloaders/optiboot/optiboot.c @@ -213,7 +213,7 @@ int main(void) { // If not, uncomment the following instructions: // cli(); // SP=RAMEND; // This is done by hardware reset - // asm volatile ("clr __zero_reg__"); + asm volatile ("clr __zero_reg__"); uint8_t ch; -- cgit v1.2.3-18-g5258